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notice: dtla sensitive information has been withheld from this data sheet. see section 2.1 for details. PDI1394L41 1394 content protection av link layer controller preliminary specification supersedes data of 1999 sep 30 2000 apr 15 integrated circuits
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 i 1.0 features 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0 description 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.0 quick reference data 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 ordering information 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0 pin configuration 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.0 functional diagram 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 internal block diagram 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0 application diagram 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.0 pin description 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 host interface 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2 av interface 1 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.3 av interface 2 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.4 phy interface 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.5 other pins 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0 recommended operating conditions 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.0 absolute maximum ratings 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.0 functional description 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 overview 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2 av interface and av layer 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.1 iec 61883 international standard 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.2 cip headers 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.3 the av interface 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.4 content protection 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.5 mlan support 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.6 sy sync support 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.2.7 programmable buffer memory 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3 bushold and link/phy single capacitor galvanic isolation 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.1 bushold 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.3.2 single capacitor isolation 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.4 power management 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5 the host interface 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.1 read accesses 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.2 write accesses 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.3 big and little endianness, data invariance, and data bus width 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.4 accessing the asynchronous packet queues 17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.5.5 the cpu bus interface signals 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6 the asynchronous packet interface 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6.1 reading an asynchronous packet 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6.2 link packet data formats 26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.7 interrupts 40 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.0 register map 41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1 link control registers 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.1 id register (idreg) base address: 0x000 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.2 general link control (lnkctl) base address: 0x004 46 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.3 link /phy interrupt acknowledge (lnkphyintack) base address: 0x008 48 . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.4 link / phy interrupt enable (lnkphyinte) base address: 0x00c 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.5 cycle timer register (cyctm) base address: 0x010 49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.6 phy register access (phyacs) base address: 0x014 50 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.7 global interrupt status and tx control (globcsr) base address: 0x018 50 . . . . . . . . . . . . . . . . . . . . . . . . . 13.1.8 timer (timer) base address: 0x01c 51 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2 av (isochronous) transmitter and receiver registers 52 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.1 isochronous transmit packing control and status (itxpkctl) base address: 0x020 52 . . . . . . . . . . . . . . . 13.2.2 common isochronous transmit packet header quadlet 1 (itxhq1) base address: 0x024 53 . . . . . . . . . . . 13.2.3 common isochronous transmit packet header quadlet 2 (itxhq2) base address: 0x028 53 . . . . . . . . . . .
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 ii 13.2.4 isochronous transmitter interrupt acknowledge (itxintack) base address: 0x02c 54 . . . . . . . . . . . . . . . . 13.2.5 isochronous transmitter interrupt enable (itxinte) base address: 0x030 54 . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.6 isochronous transmitter control register (itxctl) base address: 0x34 55 . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.7 isochronous transmitter memory status (itxmem) base address: 0x038 55 . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.8 isochronous receiver unpacking control (irxpkctl) base address: 0x040 56 . . . . . . . . . . . . . . . . . . . . . . 13.2.9 common isochronous receiver packet header quadlet 1 (irxhq1) base address: 0x044 57 . . . . . . . . . . 13.2.10 common isochronous receiver packet header quadlet 2 (irxhq2) base address: 0x048 57 . . . . . . . . . 13.2.11 isochronous receiver interrupt acknowledge (irxintack) base address: 0x04c 58 . . . . . . . . . . . . . . . . . 13.2.12 isochronous receiver interrupt enable (irxinte) base address: 0x050 58 . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.13 isochronous receiver control register (irxctl) base address: 0x054 59 . . . . . . . . . . . . . . . . . . . . . . . . . . 13.2.14 isochronous receiver memory status (irxmem) base address: 0x058 60 . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3 asynchronous control and status interface 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.1 asynchronous rx/tx control (asyctl) base address: 0x080 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.2 asynchronous rx/tx memory status (asymem) base address: 0x084 61 . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.3 asynchronous transmit request next (tx_rq_next) base address: 0x088 62 . . . . . . . . . . . . . . . . . . . . . . 13.3.4 asynchronous transmit request last (tx_rq_last) base address: 0x08c 62 . . . . . . . . . . . . . . . . . . . . . . 13.3.5 asynchronous transmit response next (tx_rp_next) base address: 0x090 62 . . . . . . . . . . . . . . . . . . . . . 13.3.6 asynchronous transmit response last (tx_rp_last) base address: 0x094 62 . . . . . . . . . . . . . . . . . . . . . 13.3.7 asynchronous receive request (rreq) base address: 0x098 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.8 asynchronous receive response (rrsp) base address: 0x09c 63 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.9 asynchronous rx/tx interrupt acknowledge (asyintack) base address: 0x0a0 63 . . . . . . . . . . . . . . . . . . 13.3.10 asynchronous rx/tx interrupt enable (asyinte) base address: 0x0a4 64 . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.11 rdi register base address: 0x0b0 64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.3.12 shadow register (shadow_reg) base address: 0x0f4 65 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4 indirect address registers 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.1 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2 indirect address register (indaddr) base address: 0x0f8 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.3 indirect data register (inddata) base address: 0x0fc 66 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5 indirect address registers 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.5.1 registers for fifo size programming 67 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.0 dc electrical characteristics 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14.1 pin categories 70 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15.0 ac characteristics 71 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.0 timing diagrams 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.1 av interface operation 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.2 av interface critical timings 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.3 phy-link interface critical timings 73 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.4 host interface critical timings 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.5 cyclein/cycleout timings 74 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16.6 reset timings 75 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 1 2000 apr 15 1.0 features ? ieee1394.a and ieee13941995 standard link layer controller ? hardware support for the iec61883 international standard of digital interface for consumer electronics ? interface to any ieee 13941995 or 1394.a physical layer interface ? 5v tolerant i/os ? single 3.3v supply voltage ? full-duplex isochronous operation ? operates with 400/200/100 mbps physical layer devices ? 12k byte fully programmable fifo pool for isochronous and asynchronous data ? supports single capacitor isolation mode and ieee 13941995, annex j. isolation ? 6-field deep syt buffer added to enhance real-time isochronous synchronization using the avfsync pin ? generates its own av port clocks under software control. select one of three frequencies: 24.576, 12.288, or 6.144 mhz ? hardware support for the a5co content protection method ? on chip timer resources ? flexible 8/16 bit multiplexed/non-multiplexed host interface ? parallel av interface ? fast 56-bit m6 cipher/decipher blocks capable of operating at over 80 mbps ? hardware authentication acceleration to reduce software processor loading ? highly configurable 12 k byte fifo 2.0 description the PDI1394L41, philips semiconductors full duplex 1394 audio/video (av) link layer controller, is an ieee 13941995 compliant link layer controller featuring 2 embedded av layer interfaces. the av layers are designed to encrypt and pack, or unpack and decrypt application data packets for transmission over the ieee1394 bus using isochronous data transfers and the a5co content protection method. the application data is packetized according to the iec 61883 international standard of interface for consumer electronic audio/video equipment. both av layer interfaces are byte-wide ports capable of accommodating various mpeg2 and dvc codecs. a flexible host interface is provided for internal register configuration as well as performing asynchronous data transfers. both 8 bit and 16 bit wide data paths, as well as multiplexed/non-multiplexed access modes are supported. the PDI1394L41 is powered by a single 3.3v power supply and the inputs and outputs are 5v tolerant. it is available in the lqfp144 package. 2.1 use restrictions due to rules set forth by the digital transmission licensing administrator (dtla) information concerning some features of the l41 is the subject of a license issued by the dtla. that information has been omitted from this data sheet and is available only to dtla licensees on a restricted distribution basis. in order to obtain a copy of the information, licensed parties should contact philips semiconductors at 1394@philips.com and request data sheet addendum al41-1. upon verification of the requestor's dtla license status, a paper copy of the addendum will be sent to the dtla listed responsible person within the requesting company. distribution of samples and sales of the l41 chip are likewise restricted to dtla licensees. for information pertaining to the procurement of a dtla license please consult the dtla website at dtcp.com. 3.0 quick reference data gnd = 0v; t amb = 25 c symbol parameter conditions min typ max unit v dd functional supply voltage range 3.0 3.3 3.6 v i dd supply current @ v dd = 3.3v operating 110 150 ma sclk device clock 49.147 49.152 49.157 mhz 4.0 ordering information packages temperature range outside north america north america pkg. dwg. # 144-pin lqfp144 0 c to +70 c PDI1394L41be PDI1394L41be sot4861 note: this datasheet is subject to change. please visit out internet website www.semiconductors.philips.com/1394 for latest changes.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 2 5.0 pin configuration pin function 1 hif d15 2 hif d14 3 hif d13 4 hif d12 5 gnd 6v dd 7 hif d11 8 hif d10 9 hif d9 10 hif d8 11 gnd 12 v dd 13 hif ad7 14 hif ad6 15 hif ad5 16 hif ad4 17 gnd 18 v dd 19 hif ad3 20 hif ad2 21 hif ad1 22 hif ad0 23 gnd 24 v dd 25 hif a8 26 hif a7 27 hif a6 28 hif a5 29 hif a4 30 hif a3 31 hif a2 32 hif a1 33 hif a0 34 gnd 35 v dd 36 hif csn pin function 37 hif wrn 38 hif intn 39 hif ale 40 hif rdn 41 hif wait 42 resetn 43 gnd 44 v dd 45 hif 16bit 46 hif mux 47 1394 mode 48 pd 49 reserved 50 reserved 51 reserved 52 reserved 53 gnd 54 v dd 55 clk50 56 cyclein 57 cycleout 58 reserved 59 reserved 60 gnd 61 v dd 62 testpin 63 testpin 64 testpin 65 reserved 66 reserved 67 reserved 68 reserved 69 gnd 70 v dd 71 reserved 72 reserved pin function 73 phy d7* 74 phy d6* 75 phy d5* 76 phy d4* 77 gnd 78 v dd 79 phy d3* 80 phy d2* 81 phy d1* 82 phy d0* 83 gnd 84 v dd 85 phy ctl1* 86 phy ctl0* 87 lreq 88 sclk* 89 gnd 90 v dd 91 lps* 92 linkon 93 ison 94 gnd 95 v dd 96 av1err0 97 av1err1 98 av1endpck 99 av1clk 100 av1fsync 101 av1 sy 102 av1valid 103 av1sync 104 av1emio 105 av1emi1 106 gnd 107 v dd 108 av1d0 pin function 109 av1d1 110 av1d2 111 av1d3 112 gnd 113 v dd 114 av1d4 115 av1d5 116 av1d6 117 av1d7 118 av1ready 119 gnd 120 v dd 121 av2err0/ltlend 122 av2err1/datinv 123 av2endpck 124 av2clk 125 av2fsync 126 av2 sy 127 av2valid 128 av2sync 129 av2emi0 130 av2emi1 131 gnd 132 v dd 133 av2d0 134 av2d1 135 av2d2 136 av2d3 137 gnd 138 v dd 139 av2d4 140 av2d5 141 av2d6 142 av2d7 143 av2ready 144 reserved sv01020 lqfp 144 1 36 37 73 72 109 108 * indicates pin equipped with internal bus hold circuit activated by the state of the ison pin.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 3 6.0 functional diagram av layer 1 host phy hif a[8:0] hif d[15:8] hif wrn hif rdn hif csn hif intn resetn cyclein cycleout av1 d[7:0] av1clk av1sync av1fsync av2fsync av1endpck av1err0 phy d[0:7] phy ctl[0:1] lreq ison sclk vdd gnd PDI1394L41 ieee 1394 content protection av link layer controller av1valid sv01021 av layer 2 av2d[7:0] av2clk av2valid av2sync av2endpck av2err0/ltlend hif ad[7:0] hif ale hif mux hif 16bit hif wait pd av1emi[1:0] av1 sy av2emi[1:0] av2 sy linkon lps av1ready av2ready av1err1 av2err1/datainv 1394mode clk50 7.0 internal block diagram hif a[8:0] hif ad[7:0] hif wrn hif rdn hif csn hif intn resetn cyclein cycleout av1 d[7:0] av1clk av1sync av1fsync av1endpck av1err0 phy d[0:7] phy ctl[0:1] lreq ison sclk av1valid av1 layer isochronous transmitter/ receiver 12kb buffer memory (isoch & async packets) link core 8-bit interface async transmitter and receiver control and status registers av2 d[7:0] av2clk av2sync av2fsync av2endpck av2valid av2 layer isochronous transmitter/ receiver av layer2 av layer1 av2err0/ltlend sv01022 hif d[15:8] hif wait hif ale hif mux hif 16bit note : there is one isochronous receiver and one isochronous transmitteretherefore, when either avport is set to transmit, the other avport is automatically set to receive linkon pd lps av1ready av1emi[1:0] av2ready av2emi[1:0] av1err1 av2err1/datainv av1sy av2sy host 1394mode
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 4 8.0 application diagram mpeg or dvc decoder PDI1394L41 av link av interface pdi1394pxx phy phylink interface host controller data 16/ address 9/ interrupt & control 1394 cable interface mpeg or dvc decoder av interface sv01023 9.0 pin description 9.1 host interface pin no. pin symbol i/o name and function 13, 14, 15, 16, 19, 20, 21, 22 hif ad[7:0] i/o host interface data 7 (msb) through 0. byte wide data path to internal registers. 1, 2, 3, 4, 7, 8, 9, 10 hif d[15:8] i/o host interface data 15 (msb) through 8. only used in 16 bit access mode (hif 16bit = high). 26, 27, 28, 29, 30, 31, 32, 33 hif a[7:0] i/o host interface address 0 through 8. provides the host with a byte wide interface to internal registers. see description of host interface for addressing rules (section 12.5). 25 hif a8 i control bit used to indicate the first byte/word of a read function or the last byte/word of a write function so that the data quadlet is fetched or stored. see section 12.5 for more information regarding the host interface. 36 hif csn i chip select (active low). host bus control signal to enable access to the fifo and control and status registers. 37 hif wrn i write enable. when asserted (low) in conjunction with hif csn, a write to the PDI1394L41 internal registers is requested. (note: hif wrn and hif rdn : if these are both low in conjunction with hif csn, then a write cycle takes place. this can be used to connect cpus that use r/w_n line rather than separate rd_n and wr_n lines. in that case, connect the r/w_n line to the hif wrn and tie hif rdn low.) 38 hif intn o interrupt (active low). indicates a interrupt internal to the PDI1394L41. read the general interrupt register for more information. this pin is open drain and requires a 1k pull-up resistor. 39 hif ale i address latch enable. used in multiplex mode only. 40 hif rdn i read enable. when asserted (low) in conjunction with hif csn, a read of the PDI1394L41 internal registers is requested. 41 hif wait o wait signal. signals host interface in wait condition when hi. see section 12.5. 42 resetn i reset (active low). the asynchronous master reset to the PDI1394L41. 45 hif 16bit i host interface mode pin. when low hif operates in 8 bit mode. when high hif operates in 16 bit mode. 46 hif mux i host interface mode pin. when low hif operates in non-multiplex mode, when high hif operates in multiplex mode. when high, the low-order eight address bits are multiplexed with data on hif ad[7:0], otherwise they are non-multiplexed and supplied on a[7:0].
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 5 9.2 av interface 1 note : this av interface may be configured to transmit or receive according to the condition of adirav1o bit in globcsr register (0x018)edefault is transmit. pin no. pin symbol i/o name and function 96 av1err0 o crc error. indicates bus packet delivered on av1 d[7:0] had a crc error; the current av packet is unreliable. 97 av1err1 o sequence error. indicates at least one source packet was lost before the current av1 d [7:0] data. 98 av1endpck i end of application packet indication from data source. required only if input packet is not multiple of 4 bytes. it can be tied low for data packets that are 4*n in size. 99 av1clk i/o external application clock. rising edge active. this pin can be programmed to be an output and the application clock. depending on the configuration of av port 1 as transmitter or receiver, the output enable is located in the itxpkctl register (address 0x020) or irxpkctl register (address 0x040). 100 av1fsync i/o programmable frame sync, is set to input when av interface 1 is a transmitter and to output when the interface is configured as a receiver. when the pin is an input, it is used to designate a frame of data for digital video (dv). the signal is time stamped and transmitted in the syt field of itxhq2. when set to an output, the signal is derived from syt field of irxhq2. 101 av1 sy i/o sy value. when port av1 is configured as a transmitter, this pin is an input. when the av port is configured to as a receiver, the pin is an output. see the description for bit 0 of the itxctl (0x034) and irxctl (0x054) registers. 102 av1valid i/o indicates data on av1 d [7:0] is valid. 103 av1sync i/o indicates that the data currently being clocked by the source under the condition of av1valid is the start of an application packet. if the av interface is configured as a receiver, then it will assert av1sync when an application packet becomes available and persist until the first data of the packet is clocked out. thus, av1valid may last for more than one cycle, but for exactly one cycle in which av1valid is asserted. 105, 104 av1emi[1:0] o encryption mode indication pins. outputs encryption mode when this av port is in receive state with decipher enabled. 117, 116, 115, 114, 111, 110, 109, 108 av1 d[7:0] i/o audio/video data 7 (msb) through 1. part of byte-wide interface to the av layer 1. i when the av port is configured as a receiver, this pin is an input. this is a flow control signal that allows the destination to indicate whether it is able to accept data flowing across av interface 1. the av interface responds to an inactive av1ready by not asserting av1valid, and thereby withholding data. the av1ready signal is processed through one level of pipelining, which means that the av link will accept data on the cycle in which av1ready is de-asserted and will not accept data on the cycle in which av1ready is asserted. 118 av1ready o when the av port is configured to transmit, this pin is an output. this is a flow control signal that allows the destination to indicate whether it is able to accept data flowing across av interface 1. the source of data, an external entity, responds to an inactive av1ready by not asserting av1valid, and thereby withholding data. the av1ready signal should be processed by the sink through one level of pipelining, which means that the receiver must be able to accept data on the cycle in which av1ready is de-asserted. the receiving interface does not have to accept data on the cycle in which av1ready is asserted.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 6 9.3 av interface 2 note : this av interface may be configured to transmit or receive according to the condition of adirav1o bit in globcsr registeredef ault is receive. pin no. pin symbol i/o name and function 121 av2err0/ ltlend i/o crc error, indicates bus packet containing av2 d [7:0] had a crc error, the current av packet is unreliable. this pin is also used to input the mode of ltlend (little endian) bit after a chip reset. an appropriate pull-up or pull-down resistor (22 k w recommended) should be connected to place the pin in the desired state during reset. please see details related to use of the ltlend bit in the ahost interfaceo section (of the datasheet (section 12.5). 122 av2err1/ datinv i/o sequence error. indicates at least one source packet was lost before the current av2 d [7:0] data. this pin is also used to input the mode of datinv (data invariant) bit after a chip reset. an appropriate pull-up or pull-down resistor (22 k w recommended) should be connected to place the pin in the desired state during reset. please see details related to use of the datinv bit in the ahost interfaceo section (of the datasheet (section 12.5). 123 av2endpck i end of application packet indication from data source. required only if input packet is not multiple of 4 bytes. it can be tied low for data packets that are 4*n in size. 124 av2clk i/o external application clock. rising edge active. this pin can be programmed to be an output and the application clock. depending on the configuration of av port 2 as transmitter or receiver, the output enable is located in the itxpkctl register (address 0x020) or irxpkctl register (address 0x040). 125 av2fsync i/o programmable frame sync, is set to input when av interface 2 is a transmitter, and to output when the interface is configures as a receiver. when the pin is an input, it is used to designate a frame of data for digital video (dv). the signal is time stamped and transmitted in the syt field of itxhq2. when set to an output, the signal is derived from syt field of irxhq2. 126 av2 sy i/o sy value: when port av2 is configured as a transmitter, this pin is an input. when the av port is configured to as a receiver, the pin is an output. see the description for bit 0 of the itxctl (0x034) and irxctl (0x054) registers. 127 av2valid i/o indicates data on av2 d [7:0] is valid. 128 av2sync i/o indicates that the data currently being clocked by the source under the condition of av2valid is the start of an application packet. if the av interface is configured as a receiver, then it will assert av2sync when an application packet becomes available and persist until the first data of the packet is clocked out. thus, av2valid may last for more than one cycle, but for exactly one cycle in which av2valid is asserted. 130, 129 av2emi[1:0] o encryption mode indication pins. outputs encryption mode when this av port is in receive state with decipher enabled. 142, 141, 140, 139, 136, 135, 134, 133 av2 d[7:0] i/o audio/video data 7 (msb) through 0. part of byte-wide interface to the av layer 2. i when the av port is configured as a receiver, this pin is an input. this is a flow control signal that allows the destination to indicate whether it is able to accept data flowing across av interface 2. the av interface responds to an inactive av2ready by not asserting av2valid, and thereby withholding data. the av2ready signal is processed through one level of pipelining, which means that the av link will accept data on the cycle in which av2ready is de-asserted and will not accept data on the cycle in which av2ready is asserted. 143 av2ready o when the av port is configured to transmit, this pin is an output. this is a flow control signal that allows the destination to indicate whether it is able to accept data flowing across av interface 2. the source of data, and external entity, responds to an inactive av2ready by not asserting av2valid, and thereby withholding data. the av2ready signal should be processed by the sink through one level of pipelining, which means that the receiver must be able to accept data on the cycle in which av2ready is de-asserted. the receiving interface does not have to accept data on the cycle in which av2ready is asserted.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 7 9.4 phy interface pin no. pin symbol i/o name and function 82, 81, 80, 79, 76, 75, 74, 73 phy d[0:7] i/o data 0 (msb) through 7 (note: to preserve compatibility to the specified link-phy interface of the ieee 13941995 standard, annex j, bit 0 is the most significant bit). data is expected on av d[0:1] for 100mb/s, av d[0:3] for 200mb/s, and av d[0:7] for 400mb/s. see ieee 13941995 standard, annex j for more information. 86, 85 phy ctl[0:1] i/o control lines between link and phy. see 1394 specification for more information. 47 1394 mode i 13941995 annex j phy (high), or 1394.a phy (low) 87 lreq o link request. bus request to access the phy. see ieee 13941995 standard, annex j for more information. (used to request arbitration or read/write phy registers). 88 sclk i system clock. 49.152mhz input from the phy (the phy-link interface operates at this frequency). 91 lps o link power status. 92 linkon i l41 generates a host interrupt when this pin receives a link on signal from the phy. interrupt is a request from another node for the l41 to be powered up (see pd pin). 93 ison i isolation mode. this pin is asserted (low) when an annex j type isolation barrier is used. see ieee 13941995 annex j. for more information. when tied high, this pin enables internal bushold circuitry on the affected phy interface pins (see below). active bushold circuits allow either the direct connection to phy pins or the use of the single capacitor isolation mode. 9.5 other pins pin no. pin symbol i/o name and function 5, 11, 17, 23, 34, 43, 53, 60, 69, 77, 83, 89, 94, 106, 112, 119, 131, 137 gnd ground reference 6, 12, 18, 24, 35, 44, 54, 61, 70, 78, 84, 90, 95, 107, 113, 120, 132, 138 v dd 3.3v 0.3v power supply 48 pd 1,2,3,4 i power down. when asserted (high), the av link goes into a low power mode and de-asserts the lps pin. when in this state, reads and writes to the registers are not allowed. the av link will resume operation when pd is de-asserted (low), all register settings and configurations are restored to their pre power down values. 49, 50, 51, 52, 58, 59, 65, 66, 67, 68, 71, 72 144 reserved na these pins are reserved for factory testing. for normal operation they should be connected to ground. 55 clk50 o auxiliary clock, value is sclk (usually 49.152 mhz) 56 cyclein i provides the capability to supply an external cycle timer signal for the beginning of 1394 bus cycles. 57 cycleout o reproduces the 8khz cycle clock of the cycle master. 62, 63, 64 testpin test pins. these signals must be connected to ground. notes: before asserting the rpl bit, swpd or setting the pd pin high, the user should assure that the link chip is in the following st ate of operation: 1. the isochronous transmit fifo is not receiving data for transmission 2. the isochronous transmitter is disabled 3. no asynchronous packets are being generated for transmission 4. both the async request and response queues are empty
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 8 10.0 recommended operating conditions symbol parameter conditions limits unit symbol parameter conditions min. max. unit v cc dc supply voltage 3.0 3.6 v v i input voltage 0 5 v v ih high-level input voltage 2.0 v v il low-level input voltage 0.8 v i oh high-level output current 4 ma i ol low-level output current 4 ma dt/dv input transition rise or fall time 0 20 ns/v t amb operating ambient temperature range 0 +70 c sclk system clock 49.147 49.157 mhz avclk av interface clock 0 24 mhz t r input rise time 10 ns t f input fall time 10 ns 11.0 absolute maximum ratings 1, 2 in accordance with the absolute maximum rating system (iec 134). voltages are referenced to gnd (ground = 0v). symbol parameter conditions limits unit symbol parameter conditions min max unit v dd dc supply voltage 0.5 +4.6 v i ik dc input diode current 50 ma v i dc input voltage 0.5 +5.5 v i ok dc output diode current 50 ma v o dc output voltage 0.5 v dd +0.5 v i o dc output source or sink current 50 ma i gnd , i cc dc v cc or gnd current 150 ma t stg storage temperature range 60 150 c t amb operating ambient temperature 0 70 c p tot power dissipation per package 0.6 w notes: 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditionso is not implied. exposur e to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create ju nction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not excee d 150 c.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 9 12.0 functional description 12.1 overview the PDI1394L41 is an ieee13941995 and ieee1394.a compliant link layer controller. it provides a direct interface between a 139 4 bus and various mpeg2 and dvc codecs. the av link maps and unmaps av data streams and similar data onto 1394 isochronous packets. data can be ciphered or deciphered according to the `5c' standard method of content protection. the av link also provides an 8 bit or 16 bit wide host interface for an attached microcontroller. through the host interface port, the host controller can configure the av layer for transmission or reception of av datastreams. the host interface port also allows the host controller to transmit and receive 1394 asynchronous data packets. 12.2 av interface and av layer the av interface and av layer format aapplication packetso according to the iec 61883 specification for isochronous transport o ver the 1394 network. the av transmitter and receiver within the av layer perform all the functions required to pack and unpack av packet da ta for transfer over a 1394 network. once the av layer is properly configured for operation, no further host controller service should be requi red. the operation of the av layer is full-duplex, i.e., the av layer can receive and transmit av packets on the same bus cycle. 12.2.1 iec 61883 international standard the PDI1394L41 is specifically designed to support the iec61883 international standard of digital interface for consumer electr onic audio/video equipment. the iec specification defines a scheme for mapping various types of av datastreams onto 1394 isochronous data packets. the standard also defines a software protocol for managing isochronous connections in a 1394 bus called connection man agement protocol (cmp). it also provides a framework for transfer of functional commands, called function control protocol (fcp). 12.2.2 cip headers a feature of the iec61883 international standard is the definition of common isochronous packet (cip) headers. these cip header s contain information about the source and type of datastream mapped onto the isochronous packets. the av layer supports the use of cip headers. cip headers are added to transmitted isochronous data packets at the av data sour ce. when receiving isochronous data packets, the av layer automatically analyzes their cip headers. the analysis of the cip headers dete rmines the method the av layer uses to unpack the av data from the isochronous data packets. the information contained in the cip headers is accessible via registers in the host interface. (see iec61883 international standard of digital interface for consumer electronic audio/video equipment for more details on cip headers). 12.2.3 the av interface the av link's 8-bit parallel interface is synchronous with avxclk, and was designed to interface with various mpeg-2 and dvc co decs. the av interface port buffer, if so programmed, can time stamp incoming av packets. the av packet data is stored in the embedded me mory buffer, along with its time stamp information. after the av packet has been written into the av layer, the av layer creates an isochron ous bus packet with the appropriate cip header. the bus packet along with the cip header is transferred over the appropriate isochronous chann el/packet. the size and configuration of isochronous data packet payload transmitted is determined by the av layer's configuration registe rs accessible through the host interface. the av interface port waits for the assertion for avxvalid and avxsync. avxsync is aligned with the rising edge of avxclk and t he first byte of data on avxdata[7:0]. the duration of avxsync is one avxclk cycle. avxsync signals the av layer that the transfer of an av packet has begun. at the time the avxsync is asserted, the av layer creates a new time stamp in the buffer memory. (this only happens if so configured. the dvc format does not require these time stamps). the time stamp is then transmitted as part of the source packet header. this allows the av receiver to provide the av packet for output at the appropriate time. only one avsync pulse is allowed per applic ation packet; if additional sync pulses are presented before the full packet is inputted, a new packet will be started and the previously inputt ed packet data will be discarded (and not transmitted) in conjunction with the input error interrupt bit (inperr, bit 3 of register 0x02c) being se t to flag the error. an additional synchronization mechanism is defined by the iec 61883 specification, called frame sync. the frame synchronization signal avxfsync is time stamped and placed in the syt field of the cip header. the default delay value for the frame sync is 3 bus cyc le times (duration of 125 m s each) in the future, and is transmitted on the very next isochronous cycle regardless of available data. the PDI1394L41 allows this value to be programmable from 2 to 4 cycle times (see section 13.2.1). additionally, for some audio applications, t he syt value can be programmed to be appended only to isochronous cycles that have application data attached to them. this mode is enabled via t he `mlan' bit (again, see section 13.2.1). when the mlan mode is enabled, two additional cycle delays are automatically added to the syt_ delay value (bits 6 and 5 of the itxpkclt register). on the receiver side, when the syt stamp matches the cycle timer register, a pulse is generated on the avxfsync output. the timing for avxfsync is independent of avxclk. some applications would like to create their own transmit timestamps independent of the av layer. on receive, these application s would like to process the embedded time stamps instead of allowing the av layer to process these time stamps. this can be accommodated via th e enxtmstmp bit in the itxpkctl register for transmit and dis_tsc bit in the irxpkctl register for receive. in conjunction with t his mode, additional means of flow control are enabled via the avxready signal.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 10 port dir avxready description transmit out the l41 is prepared to receive a byte. the attached device will not assert avvalid for any cycle in which avxrdy is false. receive in the attached device is prepared to receive a byte. the l41 will not assert avxvalid for any cycle in which avxready is false. when the av port is configured as a receiver, the avxsync signal will be asserted as soon as the PDI1394L41 avx port has an app lication packet available for delivery (independent of avxready) and will remain asserted until the first byte of the application packet is clocked from the av port. 12.2.4 content protection the av layer incorporates features to implement the digital transmission copy protection (dtcp) scheme that is specified by the digital transmission licensing authority (dtla). the dtcp specification consists of two primary functions: stream ciphering and authent ication. refer to a5c digital transmission content protection specification volume 1o for more details about the dtcp scheme. on the av link stream ciphering is accomplished by internal 56 bit m6 content cipher and decipher blocks. to ease software deve lopment effort and reduce the loading on the controlling processor, the link chip also includes a cryptographic accelerator capable of doing e lliptic curve multiplications and sign and verify operations. due to the size and number of operands for the m6 and cryptographic accelerator blocks, the host interface register set has bee n extended to provide additional control and data registers. these extensions have been implemented via an indirect addressing mechanism. thi s mechanism allows software written for previous versions of the av link (pdi1394l21 and pdi1394l11) to operate on the PDI1394L41. note, ho wever, that some extensions to the interrupt registers were made to accommodate interrupts originating from the content protection block. for a full description of the use of the l41's content protection features please see data sheet addendum al411. al411 addend um can be requested from philips by dtla licensees by e-mailing 1394@philips.com . one paper copy of this addendum is available to each dtla licensee after verification of license status. please see section 2.1 of this data sheet for further information. dtla license information is available at dtcp.com.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 11 12.2.5 mlan support the av transmitter has some additional features to support mlan (iec 61883-6). these are enabled by setting bit 30 of itxpkctl (0x020) to logic 1. at the rising edge of avxfsync, a syt time stamp will be generated and written into the syt queue of the isochronous t ransmitter. this stamp will point to a time in the future dictated by the following formula: syt[15:12] = cyctm[15:12] + programmed syt_delay value + 2 syt[11:0] = cyctm[11:0] the additional delay of two cycles is specific to this mlan mode. the oldest syt time stamp in the syt queue will be sent first , but only when accompanied by a data payload. any pending syt time stamp will be held until the next non-empty bus packet is sent. at the mome nt of transmission, the syt time stamp should at least point one cycle in the future. if it points to a time that is less than one cy cle in the future, it will be discarded. the syt queue in the isochronous transmitter can store 4 entries, the syt queue in the isochronous receiver can store six entri es. this supports the case where an 8 khz signal is applied to avxfsync, and mlan = 1, and syt_delay = 2. assuming there is data on ever y cycle, the receiver will receive an syt time stamp each cycle with the first syt time stamp pointing just less than six cycles in the future. when the syt queue in the isochronous receiver is full, then the most recently received syt time stamp is overwritten with the next arri ving syt time stamp. 12.2.6 sy sync support this feature supports the 1394 digital camera specification. the state of this pin will be reflected in the sy bit (itxctl regi ster 0x034) and will be transmitted along with the isochronous data block that was entered with it. the intended use of this pin is to signal the st art of a new frame of video in the isochronous header section of the data payload. similarly, the isochronous receiver will assert the avxsy pin simu ltaneously with the first byte of the isochronous bus packet in which the sy value was received. note: the sy functionality is only intended to be used when the m6 cipher and de-cipher are not enabled. sv01787 av data av sync av sy figure 1. behavior of sysncr 12.2.7 programmable buffer memory the PDI1394L41 maintains six distinct buffers that are highly configurable to optimize bandwidth capabilities. buffers can be i ncreased or decreased from the default value by accessing the indirect address range of 0x100 through 0x1fc (indaddr, 0x0f8). if the av lay er is configured to transmit or receive dvb compliant mpeg-2 type data, the default isochronous (av) buffer sizes are recommended. fi fo sizes cannot be changed dynamically; after a fifo size change, transmitters and receivers must be reset. buffers can be programmed with 64 quadlet (256 byte) granularity. minimum buffer size is 64 quadlets, maximum buffer size is li mited to 11 kb. the sum of all buffers cannot exceed 12k bytes, or 3k quadlets. default buffer size buffer memory size (quadlets) asynchronous receive response fifo 256 asynchronous receive request fifo 256 asynchronous transmit response fifo 256 asynchronous transmit request fifo 256 isochronous (av) transmit buffer 1024 isochronous (av) receive buffer 1024
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 12 12.3 bushold and link/phy single capacitor galvanic isolation 12.3.1 bushold the PDI1394L41 uses an internal bushold circuit on each of the indicated pins to keep these cmos inputs from afloatingo while b eing driven by a 3-stated device or input coupling capacitor. unterminated high impedance inputs react to ambient electrical noise which cause internal oscillation and excess power supply current draw. the following pins have bushold circuitry enabled when the ison pin is in the logic a1o state: name function phy ctl0 phy control line 0 phy ctl1 phy control line 1 phy d0 phy data bus bit 0 phy d1 phy data bus bit 1 phy d2 phy data bus bit 2 phy d3 phy data bus bit 3 phy d4 phy data bus bit 4 phy d5 phy data bus bit 5 phy d6 phy data bus bit 6 phy d7 phy data bus bit 7 philips bushold circuitry is designed to provide a high resistance pull-up or pull-down on the input pin. this high resistance is easily overcome by the driving device when its state is switched. figure 2 shows a typical bushold circuit applied to a cmos input stage. two w eak mos transistors are connected to the input. an inverter is also connected to the input pin and supplies gate drive to both transist ors. when the input is low, the inverter output drives the lower mos transistor and turns it on. this re-enforces the low on the input pin. if the logic device which normally drives the input pin were to be 3-stated, the input pin would remain apulled-downo by the weak mos transistor. if the driving logic device drives the input pin high, the inverter will turn the upper mos transistor on, re-enforcing the high on the input pin. i f the driving logic device is then 3-stated, the upper mos transistor will weakly hold the input pin high. the phy's outputs can be 3-stated and single capacitor isolation can be used with the link; both situations will allow the link inputs to float. with bushold circuitry enabled, these pins are provided with dc paths to ground, and power by means of the bushold transistors; this arrangement keeps the inputs in known logical states. sv00911 input pin internal circuits figure 2. bushold circuit
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 13 12.3.2 single capacitor isolation the circuit example (figure 3) shows the connections required to implement basic single capacitor link/phy isolation. note: the isolation enablement pins on both devices are in their a1o states, activating the bushold circuits on each part. the bushol d circuits provide local dc ground references to each side of the isolating/coupling capacitors. also note that ground isolation/signal-co upling must be provided in the form of a parallel combination of resistance and capacitance as indicated in the ieee 1394 standard. iso phy pdi1394p2x c r c c 1meg w ison link PDI1394L41 application/link +3.3v isolated/phy +3.3v sv01816 c c = 1 nf; c r = 100 nf; c l = 3.3nf sclk phy d0 phy d1 phy d2 phy d3 phy d4 phy d5 phy d6 phy d7 phyctl0 phyctl1 lreq lps linkon application and link ground isolated phy ground sysclk d0 d1 d2 d3 d4 d5 d6 d7 phyctl0 phyctl1 lreq lps linkon c l link 3.3v phy 3.3v c l values of these resistors depend on phy used. see phy datasheet. c c 13k 9.1k c c c c c c c c c c c c c c c c c c c c c c also see application note an2452 for more details figure 3. single capacitor link/phy isolation 12.4 power management the PDI1394L41 implements several features for power management as noted in the p1394a draft 5.0 . these features include: 1. reset of the phy/link interface by setting the rpl bit in the lnkctl register. 2. disable of the phy/link interface caused by either setting the swpd bit in the rdi register or asserting (high) the pd pin. 3. initialization of the phy/link interface after it was disabled or reset. the application can power up the phy/link interface by deasserting the pd pin or clearing (low) the swpd in the rdi register. this will cause the l41 to produce a pulsing signal on the lps pin. when the l41 is in power down mode, reads and writes to the host inte rface will be restricted to those addressing only the rdi register (0x0b0). please see section 13.3.11 for further details. there are 3 ways to power up the l41. (1) when the application wants the 1394 node to resume operation, it simply needs to dea ssert the pd pin, or (2) clear the swpd bit in the rdi register. the link can also be awakened by another bus node sending a linkon packet to the phy of the application's node. (3) the attached phy will activate its linkon line and the l41 will see the signal and set the loa bit of the rdi register (assuming that the eloa bit is in its enabled, o1o, state). the l41 will generate an interrupt of the host processor. it will t hen be up to the host processor to decide whether to honor the linkon request of the other node. then the host processor will deassert the pd pin or clear the swpd bit in the rdi register. this activity will power up the l41 causing it to send the pulsing signal out on the lps pin whic h notifies the phychip of link activity and allows the phy to discontinue directing the link on signal to the l41. subsequently, the host proc essor must acknowledge the loa interrupt by writing a o1o to the loa bit position in the rdi register after the link on signal from the ph y has stopped.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 14 12.5 the host interface the host interface allows an 8 bit or 16 bit cpu to access all registers and the asynchronous packet queues. it is designed to be easy to use with a wide range of processors, including 8051, mips1900, st20, powerpc etc. the host interface can work with 8 bit or 16 bit wide data paths, and offers multiplexed or non-multiplexed access. there are 64 register addresses (for quadlet wide registers). to acces s bytes rather than quadlets the address space is 256 bytes, requiring 8 address lines. the use of an 8 bit or 16 bit interface introduces an inherent problem that must be solved: register fields can be more than 8 bits wide and be used (control) or changed (status) at every internal clock tick. if such a field is accessed through an 8 bit or 16 bit interfa ce it requires more than one read or write cycle, and the value should not change in between to maintain consistency. to overcome this problem accesses to the chip's internal register space are always 32 bits, and the host interface must act as a converter between the internal 32 bit accesses and external 8 bit or 16 bit accesses. this is where the shadow register (0x0f4) is used. 12.5.1 read accesses to read an internal register the host interface can make a snapshot (copy) of that specific register which is then made availab le to the cpu 8 or 16 bits at a time. the register that holds the snapshot copy of the real register value inside the host interface is called the shadow register . during an 8-bit read cycle address lines hif a0 and hif a1 are used to select which of the 4 bytes currently stored in the shadow register is output onto the cpu data bus. this selection is done by combinatorial logic only, enabling external hardware to toggle these li nes through values 0 to 3 while keeping the chip in a read access mode to get all 4 bytes out very fast (in a single extended read cycle), for example into an external quadlet register. during a 16 bit read cycle address line hif a1 is used to select which pair of 4 bytes currently sto red in the shadow register is output to the cpu bus. again the selection is by combinatorial logic, enabling external hardware to toggle hif a1 w hile keeping the chip in read access mode to get both words very quickly. this solution requires a control line to direct the host interface to make a snapshot of an internal register when needed, as w ell as the internal address of the target register. the register address is connected to input address lines hif a2..hif a7, and the update control line to input address line hif a8. to let the host interface take a new snapshot the target address must be presented on hif a2..hif a7 and h if a8 must be raised while executing a read access. the new value will be stored in the shadow register and the selected byte (hif a0, hif a1, 8 bit mode) or word (hif a1, 16 bit mode) appears on the output. not all registers can be accessed in direct address space. some of the registers are in an indirect address space, these regist ers control the fifo size and content protection system. the correct internal register space has to be selected through the host interface, usi ng directly addressable registers indaddr (0x0f8) and inddata (0x0fc). update/copy control sv01034 hif a8 hif a2..7 hif a0..1 (8 bit mode) hif a1 (16 bit mode) cpu shadow register 8/16 32 32 32 registers tr q q mux mux notes: 1. it is not required to read all 4 bytes of a register before reading another register. for example, in 8 bit mode, if only byt e 2 of register 0x54 is required a read of byte address 0x100 + (0 54) + 2 = 0x156 is sufficient. 2. the update control line does not necessarily have to be connected to the cpu address line hif a8. this input could also be co ntrolled by other means, for example a combinatorial circuit that activates the update control line whenever a read access is done for byte 0. this makes the internal updating automatic for quadlet reading. 3. reading the bytes of the shadow register can be done in any order and as often as needed. 4. it is possible to read/modify/write a register using the shadow register (0x0f4) without rewriting all 4 bytes. for example, to modify an enable bit in the fourth byte of the asynchronous interrupt enable (0x0a4), a read of location 0x100+0x0a0+3=0x1a3, followed by a writ e of the modified byte to the same location 0x100+0x0a0+3=0x1a3 is sufficient. the other bytes remain unchanged.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 15 12.5.2 write accesses to write to an internal register the host interface must collect the 4 byte values (8 bit mode) or 2 word values (16 bit mode) into a 32 bit value and then write the result to the target register in a single clock tick. this requires a register to hold the 32 bit value bein g compiled until it is ready to be written to the actual target register. this temporary register inside the host interface is called the shadow register . in 8 bit mode, address lines hif a0 and hif a1 are used to select which of the 4 bytes of the shadow register is to be written with the value on the cpu data bus. in 16 bit mode, hif a1 is used to select which half of the shadow register is to be written with the value on the cpu data bus. only one byte (8 bit mode) or one word (16 bit mode) can be written in a single write access cycle. not all registers can be accessed in direct address space. some of the registers are in an indirect address space, these regist ers control the fifo size and content protection system. the correct internal register space has to be selected through the host interface, usi ng directly addressable registers indaddr (0x0f8) and inddata (0x0fc). update/copy control hif a8 hif a2..7 hif a0..1 (8 bit mode) hif a1 (16 bit mode) cpu shadow register 8/16 32 32 registers tr q q mux mux sv01035 notes: 1. it is not required to write all 4 bytes, or both words of a register: those bytes that are either reserved (undefined) or don 't care do not have to be written in which case they will be assigned the value that was left in the corresponding byte of the shadow register from a previous write access. for example, to acknowledge an interrupt for the isochronous receiver in 8 bit mode, a single byte write to locat ion 0x100+(0x4c)+3 = 0x14f is sufficient. the value 256 represents setting hif a8=1. the host interface cannot directly access the fifos, but instead reads from/writes into a transfer register (shown as tr in the figures above). data is moved between fifo and tr by int ernal logic as soon as possible without cpu intervention. 2. the update control line does not necessarily have to be connected to the cpu address line hif a8. this input could also be co ntrolled by other means, for example a combinatorial circuit that activates the update control line whenever a write access is done for byt e 3 or the upper 16 bits. this makes the internal updating automatic for quadlet writing. 3. writing the bytes or words of the shadow register can be done in any order and as often as needed (new writes simply overwrit e the old value). 4. it is now possible to read/modify/write a register using the shadow register (0x0f4) without rewriting all 4 bytes. for examp le, to modify an enable bit in the fourth byte of the asynchronous interrupt enable (0x0a4), a read of location 0x100+0x0a0+3=0x1a3, followed by a write of the modified byte to the same location 0x100+0x0a0+3=0x1a3 is sufficient. the other bytes remain unchanged.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 16 12.5.3 big and little endianness, data invariance, and data bus width the host interface offers programmable endianness, data invariance, and selectable 8 and 16 bit data widths. ltlend (pin 121) a nd datinv (pin 122) are multiplexed configuration pins that will be sampled on the trailing edge of reset; the states of these pins are e stablished by connecting each pin to the proper logic state, ground or v dd , through a resistor, 22 k w is recommended. to verify the configuration, the shadow register (0x0f4) will be preset to a value of 0x0f0a0500 after a power reset. table 1 describes the configurations. table 1. configuration possible combinations ltlend (little endian) datinv (data invariant) hif 16bit result 1 1 see table 2 byte/word address is reversed 1 0 1 bytes are swapped within the word 0 x 1 16-bit data bus, address as in pdi1394l21 0 x 0 8-bit data bus, address as in pdi1394l21 table 2. explanation of the mode littleend = 1, datainvariant = 1 hif16 = 0 hif16 = 1 outside address (a1, a0) inside address (a1, a0) outside address (a1, a0) inside address (a1, a0) 00 11 0x 1x 01 10 0x 1x 10 01 1x 0x 11 00 1x 0x it is important to note that some operands in the indirect address space consist of more than one quadlet. for these operands, the lowest address always contains the most significant quadlet. in bit endian mode and datainv = 0, the bytes in each quadlet are numbered 0..3 from left (most significant) to right (least si gnificant) as shwon in figure 4. to access a register in 8 bit hif mode, at address n the cpu should use addresses e: e = n ; to access the upper 8 bits of the register. e = n + 1 ; to access the upper middle 8 bits of the register. e = n + 2 ; to access the lower middle 8 bits of the register. e = n + 3 ; to access the lower 8 bits of the register. to access a register in 16 bit hif mode, at internal address n, the cpu should use addresses e: e = n ;to access the upper 16 bits of the register e = n + 2 ;to access the lower 16 bits of the register sv00656 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 byte 0 byte 1 byte 3 3130 byte 2 figure 4. byte order in quadlets as implemented in the host interface, hif ltlend = low
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 17 in little endian mode and datainv = 0, the bytes in each quadlet are numbered 3. .0 from the left (most significant) to right ( least significant) as shown in figure 5. to access a register in 8 bit hif mode, at address n the cpu should use addresses e: e = n + 3 ;to access the upper 8 bits of the register e = n + 2 ;to access the upper middle 8 bits of the register e = n + 1 ;to access the lower middle 8 bits of the register e = n ;to access the lower 8 bits of the register to access a register in 16 bit hif mode, at internal address n, the cpu should used addresses e: e = n ;to access the lower 16 bits of the register e = n + 2 ;to access the upper 16 bits of the register sv01079 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 byte 3 byte 2 byte 0 3130 byte 1 figure 5. byte order in quadlets as implemented in the host interface, hif ltlend = high 12.5.4 accessing the asynchronous packet queues although entire incoming packets are stored in the receiver buffer memory they are not randomly accessible. these buffers act l ike fifos and only the frontmost (oldest) data quadlet entry is accessible for reading. therefore only one location (register address) is all ocated to each of the two receiver queues. reading this location returns the head entry of the queue, and at the same time removes it from the queue, making the next stored data quadlet accessible. with the current host interface such a read is in fact a move operation of the data quadlet from the queue to the shadow regist er. once the data is copied into the shadow register it is no longer available in the queue itself so the cpu should always read all 4 bytes, or both words, before attempting any other read access (be careful with interrupt handlers for the PDI1394L41!).
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 18 12.5.5 the cpu bus interface signals the cpu interface is directly compatible with a wide range of microcontrollers, and supports both multiplexed and non-multiplex access. it uses separate hif rdn, hif wrn, hif ale, and hif csn chip select lines. there are 9 address inputs (hif a0..hif a8) and 8 or 16 data in/out lines hif d[7:0] or hif d [15:0]. the upper 8 bits of the data in/out lines are only used when the 8/16 bit mode pin (hif16bit) is held high. the cpu is not required to run a clock that is synchronous to the 1394 base clock. the control signals will be resampled by the host interface before being used internally. in non-multiplex mode (hif mux = low), an access through the host interface starts when hif csn = 0 and either hif wrn = 0 or h if rdn = 0. typically the chip select signal is derived from the upper address lines of the cpu (address decode stage), but it could also b e connected to a port pin of the cpu to avoid the need for an external address decoder in very simple cpu systems. when both hif csn = 0 and hif rdn = 0 the host interface will start a read access cycle, so the cycle is triggered at the falling edge of either hif csn or hif rdn, whichever is later. in multiplex mode (hif mux = high), an access through the host interface starts when hif csn = 0 and either hif wrn = 0 or hif rd_n = 0. the address must now be presented on the hif ad [7:0] lines, and will be latched on the falling edge of ale. if hif rdn = 0, da ta will be offered after the falling edge of ale. if hif wrn = 0, data has to be presented by the microcontroller. in both multiplexed and non-multiplexed mode, hif wait can be used to signal to the controlling cpu that an extension of the cu rrent access cycle is needed. this allows the PDI1394L41 to work in the same address space as peripherals with a shorter access time. hif wa it will remain high for the minimum duration of the access cycle. if hif a[8] is high, hif wait will extend the access cycle to 120ns t o allow for the shadow register transfer to take place. subsequent access to the same register which does not required a[8] to be raised, can b e executed much faster. by connecting hif wait to the appropriate input on the controlling processor, the PDI1394L41 can be mapped in memo ry space with faster devices. the PDI1394L41 should not be mapped in memory space with devices that require access faster than 15 ns. hif a[7:0] can be used as a simple demultiplexer. in multiplex mode, the address on ad[7:0] will appear on a[7:0] immediately, and will remain there until the next rising edge of hif ale. sv01088 hif rd_n hif wr_n hif a8 hifa7a0 hifd15d8 hif_wait hif_mux hif16bit hif cs_n hifad7ad0 note: ale line is held low. an extended read cycle may be implemented by holding cs_n and rd_n low (active) and changing only the a7a0 address. after each new address stabilizes, wait at least t acc and read the data. the extended read cycle can be used only following a read of the first byte of the shadow register using the a8 transfer mechanism. see the section on read accesses (12.5.1). figure 6. 16 bit read cycle non-multiplexed
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 19 sv01089 hif cs_n hif rd_n hif wr_n hifa7a0 hifd15d8 hif_wait hif_mux hif16bit hifad7ad0 a8 note: ale line is held low. figure 7. 16 bit write cycle non-multiplexed
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 20 sv01090 hif cs_n hif ale ad7ad0 a7a0 hif rd_n hif wr_n hif_wait hif_mux hif16bit note: second write cycle elongated by wait signal. a8 hifd15d8 data data addr data data addr latched latched figure 8. 16 bit write cycle multiplexed
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 21 sv01091 hif cs_n hif ale hif ad7ad0 hif a7a0 hif rd_n hif wr_n hif_wait hif_mux hif16bit a8 hifd15d8 data data latched latched addr addr da ta da ta figure 9. 16 bit read cycle multiplexed
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 22 sv01772 hif cs_n hif ale ad7ad0 a7a0 hif rd_n hif wr_n hif_wait hif_mux hif16bit a8 addr data data addr latched latched figure 10. 8 bit write cycle multiplexed
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 23 sv01773 hif cs_n hif ale hif ad7ad0 hif a7a0 hif rd_n hif wr_n hif_wait hif_mux hif16bit a8 latched latched addr addr da ta da ta figure 11. 8 bit read cycle multiplexed
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 24 sv01774 hif cs_n hif rd_n hif wr_n hifa7a0 hif_wait hif_mux hif16bit hifad7ad0 a8 note: ale line is held low. figure 12. 8 bit write cycle non-multiplexed
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 25 sv01775 hif rd_n hif wr_n hif a8 hifa7a0 hif_wait hif_mux hif16bit hif cs_n hifad7ad0 note: ale line is held low. figure 13. 8 bit read cycle non-multiplexed
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 26 12.6 the asynchronous packet interface the PDI1394L41 provides an interface to asynchronous data packets through the registers in the host interface. the format of th e asynchronous packets is specified in the following sections. 12.6.1 reading an asynchronous packet upon reception of a packet, the packet data is stored in the appropriate receive fifo, either the request or response fifo. the location of the packet is indicated by either the rreqqqav or rrspqav status bit being set in the asynchronous interrupt acknowledge (asyintack ) register. the packet is transferred out of the fifo by successive reads of the asynchronous receive request (rreq) or asynchron ous receive response (rrsp) register. the end of the packet (the last quadlet) is indicated by either the rreqqlastq or rrspqlastq bit set in asyintack. attempting to read the fifo when either rreqqqav bit or rrspqqav bit is set to 0 (in the asynchronous rx/tx inter rupt acknowledge, asyintack, register) will result in a queue read error. 12.6.2 link packet data formats the data formats for transmission and reception of data are shown below. the transmit format describes the expected organizatio n for data presented to the link at the asynchronous transmit, physical response, or isochronous transmit fifo interfaces. 12.6.2.1 asynchronous transmit packet formats these sections describe the formats in which packets need to be delivered to the queues (fifos) for transmission. there are fou r basic formats as follows: item format usage transaction code (tcode) 1 no p acket data quadlet read requests 4 1 no - packet data quadlet/block write responses 2 quadlet write requests 0 2 quadlet packet quadlet read responses 6 block read requests 5 block write requests 1 block read responses 7 3 block packet lock requests 9 lock responses b hex asynchronous streams a hex 4 unformatted transmit concatenated self-id / phy packets e hex each packet format uses several fields (see names and descriptions below). more information about these fields (not the format) can be found in the 1394 specification. grey fields are reserved and should be set to zero values.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 27 table 1. asynchronous transmit fields field name description spd this field indicates the speed at which this packet is to be sent. 00=100 mbs, 01=200 mbs, and 10=400 mbs. 11 = undefined tlabel this field is the transaction label, which is used to pair up a response packet with its corresponding request packet. tlabels are also used as identifiers to associate a link data confirmation (see 12.6.2.13) with the corresponding request, response, or asynchronous stream packet. rt only value 01 = retryx is supported. tcode the transaction code for this packet. destinationid contains a node id value. destinationoffsethigh destinationoffsetlow the concatenation of these two field addresses a quadlet in the destination node's address space. rcode response code for write response packet. rcode meaning 0 node successfully completed requested operation. 13 reserved 4 resource conflict detected by responding agent. request may be retried. 5 hardware error. data not available. 6 field within request packet header contains unsupported or invalid value. 7 address location within specified node not accessible. 8fh reserved channel a channel allocated from the isochronous manager register channels_available. tag used only for asynchronous stream transmit fields values su pp lied as a pp ro p riate by the user sy used onl y for as y nchrono u s stream transmit fields . val u es s u pplied , as appropriate , b y the u ser . priority for responses, priority is set to 0000 if fair arbitration is to be used and to 0001 if priority arbitration is to be used, as allowed by the 1394a supplement to std ieee 13941995. quadlet data for quadlet write requests and quadlet read responses, this field holds the data to be transferred. data length the number of bytes requested in a block read request. datalength the number of bytes of data to be transmitted in this packet extendedtcode the tcode indicates a lock transaction, this specifies the actual lock action to be performed with the data in this packet. block data the data to be sent. if datalength=0, no data should be written into the fifo for this field. regardless of the destination or source alignment of the data, the first byte of the block must appear in the high order byte of the first quadlet. padding if the datalength mod 4 is not zero, then zero-value bytes are added onto the end of the packet to guarantee that a whole number of quadlets is sent.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 28 12.6.2.2 no-data transmit the no-data transmit formats are shown in figures 14 and 15. the first quadlet contains packet control information. the second and third quadlets contain 16-bit destination id and either the 48-bit, quadlet aligned destination offset (for requests) or the response code (for responses). destinationid spd tlabel rt tcode priority 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 destinationoffsethigh sv01080 destinationoffsetlow 0 31 30 figure 14. quadlet read request transmit format destinationid spd tlabel rt tcode priority sv01081 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rcode 31 30 0 figure 15. quadlet/block write response packet transmit format
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 29 12.6.2.3 quadlet transmit three quadlet transmit formats are shown below. in these figures: the first quadlet contains packet control information. the se cond and third quadlets contain 16-bit destination id and either the 48-bit quadlet-aligned destination offset (for requests) or the response code (for responses). the fourth quadlet contains the quadlet data for read response and write quadlet request formats, or the upper 16 bits contain the data length for the block read request format. destinationid spd tlabel rt tcode priority 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 destinationoffsethigh destinationoffsetlow quadlet data sv01082 31 30 0 figure 16. quadlet write request transmit format destinationid spd tlabel rt tcode priority 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rcode quadlet data sv01083 31 30 0 figure 17. quadlet read response transmit format
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 30 destinationid spd tlabel rt tcode priority 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 destinationoffsethigh destinationoffsetlow data length sv01084 31 30 0 figure 18. block read request transmit format
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 31 12.6.2.4 block transmit the block transmit format is shown below, this is the generic format for reads and writes. the first quadlet contains packet co ntrol information. the second and third quadlets contain the 16-bit destination node id and either the 48-bit destination offset (for requests) or the response code and reserved data (for responses). the fourth quadlet contains the length of the data field and the extended transaction code ( all zeros except for lock transaction). the block data, if any, follows the extended transaction code. destinationid spd tlabel rt tcode priority 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 destinationoffsethigh destinationoffsetlow datalength extendedtcode block data padding (if needed) sv01085 31 30 0 figure 19. block packet transmit format spd tlabel rt tcode priority 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 datalength extendedtcode block data padding (if needed) sv01086 destinationid rcode 31 30 0 figure 20. block read or lock response transmit format
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 32 12.6.2.5 unformatted transmit the unformatted transmit format is shown in figure 21. the first quadlet contains packet control information. the remaining qua dlets contain data that is transmitted without any formatting on the bus. no crc is appended on the packet, nor is any data in the first quad let sent. this is used to send phy configuration and link-on packets. note that the bit-inverted check quadlet must be included in the fifo since the av link core will not generate it. spd tlabel 1110 priority 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 unformatted packet data sv01087 31 30 00 figure 21. unformatted transmit format 12.6.2.6 asynchronous stream transmit the PDI1394L41 supports asynchronous stream as specified in ieee1394.a. the asynchronous stream packet format is shown below. t he first quadlet contains packet control information. the second quadlet contains datalength, tag, channel number, and synchronization c ode. the third quadlet contains the datalength in quadlets. the datalength can be zero for empty asynchronous stream packets. sv01050 313029282726252423222120191817161514131211109876543210 spd tlabel 1 1110 priority datalength tag channel 1010 sy block data padding (if needed) figure 22. asynchronous stream packet transmit format when a packet conforming to this format is written to either asynchronous transmit fifo, an asynchronous stream packet (identic al on the cable to an isochronous packet) will be transmitted during the asynchronous phase of a bus cycle.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 33 12.6.2.7 asynchronous receive packet formats this section describes the asynchronous receive packet formats. four basic asynchronous data packet formats and one confirmation format exist: table 2. asynchronous data packet formats item format usage transaction code 1 no p acket data quadlet read requests 4 1 no - packet data quadlet/block write responses 2 2 quadlet p acket quadlet write requests 0 2 q u adlet packet quadlet read responses 6 block read requests 5 block write requests 1 3 block packet block read responses 7 lock requests 9 lock responses b hex 4 self-id / phy packet concatenated self-id / phy packets e hex 5 confirmation packet confirmation of packet transmission 8 each packet format uses several fields. more information about most of these fields can be found in the 1394 specification. table 3. asynchronous receive fields field name description destinationid this field is the concatenation of busnumbers (or all ones for alocal buso) and nodenumbers (or all ones for broadcast) for this node. tlabel this field is the transaction label, which is used to pair up a response packet with its corresponding request packet. tlables are also used as identifiers to associate a link data confirmation (see 12.6.2.13) with the corresponding request, response, or asynchronous stream packet. rt the retry code of the received packet; see the 1394 specification. tcode the transaction code for this packet. priority the priority level for this packet (0000 for cable environment). sourceid this is the node id of the sender of this packet. destinationoffsethigh, destinationoffsetlow the concatenation of these two field addresses a quadlet in this node's address space. rcode response code for the received packet; see the 1394 specification. quadlet data for quadlet write requests and quadlet read responses, this field holds the data received. datalength the number of bytes of data to be received in a block packet. extendedtcode if the tcode indicates a lock transaction, this specifies the actual lock action to be performed with the data in this packet. block data the data received. if datalength=0, no data will be written into the fifo for this field. regardless of the destination or source alignment of the data, the first byte of the block will appear in the high order byte of the first quadlet. padding if the datalength mod 4 is not zero, then zero-value bytes are added onto the end of the packet to guarantee that a whole number of quadlets is sent. u unsolicited response tag bit. this bit is set to one (1) if the received response was unsolicited. acksent this field contains the acknowledge code that the link layer returned to the sender of the received packet. for packets that do not need to be acknowledged (such as broadcasts) the field contains the acknowledge value that would have been sent if an acknowledge had been required. the values for this field are listed in table 4 (they also can be found in the ieee 1394 standard). status this field is used for asynchronous streams. 0000 reserved. 0001 packet ok. 00101100 reserved. 1101 data crc error and/or block size mismatch have been detected. 11101111 reserved.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 34 table 4. acknowledge codes code name description 0001 ack_complete the node has successfully accepted the packet. if the packet was a request subaction, the destination node has successfully completed the transaction and no response subaction shall follow. 0010 ack_pending the node has successfully accepted the packet. if the packet was a request subaction, a response subaction will follow at a later time. this code shall not be returned for a response subaction. 0100 ack_busy_x the packet could not be accepted. the destination transaction layer may accept the packet on a retry of the subaction. 0101 ack_busy_a the packet could not be accepted. the destination transaction layer will accept the packet when the node is not busy during the next occurrence of retry phase a. 0110 ack_busy_b the packet could not be accepted. the destination transaction layer will accept the packet when the node is not busy during the next occurrence of retry phase b. 1101 ack_data_error the node could not accept the block packet because the data field failed the crc check, or because the length of the data block payload did not match the length contained in the datalength field. this code shall not be returned for any packet that does not have a data block payload. 1110 ack_type_error a field in the request packet header was set to an unsupported or incorrect value, or an invalid transaction was attempted (e.g., a write to a read-only address). 0000, 0011, 0111 1100, and 1111 reserved this revision of the av link will not generate other acknowledge codes, but may receive them from newer (1394 a) links. in that case, these new values will show up here.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 35 12.6.2.8 no-data receive the no-data receive formats are shown below. the first quadlet contains the destination node id and the rest of the packet head er. the second and third quadlet contain 16-bit source id and either the 48-bit, quadlet-aligned destination offset (for requests) or the resp onse code (for responses). the last quadlet contains packet reception status. destinationid tlabel rt tcode priority 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 destinationoffsethigh destinationoffsetlow sourceid sv00257 spd acksent 3130 figure 23. quadlet read request receive format destinationid tlabel rt tcode priority 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rcode sourceid sv00258 spd acksent 31 30 u figure 24. write response receive format
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 36 12.6.2.9 quadlet receive the quadlet receive formats are shown below. the first quadlet contains the destination node id and the rest of the packet head er. the second and third quadlets contain 16-bit source id and either the 48-bit, quadlet-aligned destination offset (for requests) or the res ponse code (for responses). the fourth quadlet is the quadlet data for read responses and write quadlet requests, and is the data length and re served for block read requests. the last quadlet contains packet reception status. destinationid tlabel rt tcode priority 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 destinationoffsethigh destinationoffsetlow sourceid quadlet data sv00259 spd acksent 31 30 figure 25. quadlet write request receive format destinationid tlabel rt tcode priority 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rcode sourceid quadlet data sv00260 spd acksent 31 30 u figure 26. quadlet read response receive format
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 37 destinationid tlabel rt tcode priority 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 destinationoffsethigh destinationoffsetlow sourceid data length sv00261 spd acksent 31 30 figure 27. block read request receive format
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 38 12.6.2.10 block receive the block receive format is shown below. the first quadlet contains the destination node id and the rest of the packet header. the second and third quadlets contain 16-bit sourceid and either the 48-bit destination offset (for requests) or the response code and reserve d data (for responses). the fourth quadlet contains the length of the data field and the extended transaction code (all zeros except for lo ck transactions). the block data, if any, follows the extended code. the last quadlet contains packet reception status. datalength extendedtcode block data padding (if needed) destinationid tlabel rt tcode priority 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 destinationoffsethigh destinationoffsetlow sourceid sv00262 spd acksent 31 30 figure 28. block write or lock request receive format destinationid tlabel rt tcode priority 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rcode sourceid datalength extendedtcode block data padding (if needed) sv00263 spd acksent 31 30 u figure 29. block read or lock response receive format
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 39 12.6.2.11 asynchronous stream receive the asynchronous streaming receive packet format is shown below. the first quadlet contains datalength, tag, and channel number for source identification, and synchronization information. the following quadlets contain (possibly zero) quadlets of block information. the last quadlet contains transmission speed and status information. asynchronous stream packets are placed in the receive response fifo. sv01052 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 131211109876543210 sy status datalength tag channum 1010 2 block data (possibly zero) spd 12.6.2.12 self-id and phy packets receive the self-id and phy packet receive formats are shown below. the first quadlet contains a synthesized packet header with a tcode of 0xe (hex). for self-id information, the remaining quadlets contain data that is received from the time a bus reset ends to the firs t subaction gap. this is the concatenation of all the self-id packets received. note that the bit-inverted check quadlet is included in the read requ est fifo and the application must check it. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 self id packet data 1110 2 0000 2 sv00264 00 acksent 3130 figure 30. self-id receive format the aacksento field will either be aack_data_erroro if a non-quadlet-aligned packet is received or there was a data overrun, or aack_completeo if the entire string of self-id packets was received. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 phy packet first quadlet 1110 2 0000 2 sv00265 31 30 figure 31. phy packet receive format for phy packets, there is a single following quadlet which is the first quadlet of the phy packet. the check quadlet has alread y been verified and is not included.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 40 12.6.2.13 link data confirmation formats after a request, response, or asynchronous stream packet is transmitted, the asynchronous transmitter assembles a link data con firmation (see figure 32) which is used to confirm the transmission to the higher layers. packets transmitted from the transmit request fifo a re confirmed by a confirmation written into the receive request fifo and packets transmitted from the transmit response fifo are confirmed by a confirmation written into the receive response fifo. outgoing packets and their confirmations are associated by their tlabels. it is the user's responsibility to assure the uniquen ess of active tlabels. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 conf tlabel 3130 1000 01 sv01051 figure 32. request and response confirmation format table 5. confirmation codes code 1 description 0 non-broadcast packet transmitted; addressed node returned no acknowledge (transaction complete). 1 broadcast packet transmitted or non-broadcast packet transmitted; addressed node returned an acknowledge complete (transaction complete). 2 non-broadcast packet transmitted; addressed node returned an acknowledge pending. 4 retry limit exceeded; destination node hasn't accepted the non-broadcast packet within the maximum number of retries (transaction complete). d 16 acknowledge data error received (transaction complete). e 16 acknowledge type error received (transaction complete). note: 1. all other codes are reserved. 12.7 interrupts the PDI1394L41 provides a single interrupt line (hif intn) for connection to a host controller. status indications from four ma jor areas of the device are collected and ored together to activate hif intn. status from four major areas of the device are collected in four s tatus registers; lnkphyintack, itxintack, irxintack, and asyintack. at this level, each individual status can be enabled to generate a chip-leve l interrupt by activating hif intn. to aid in determining the source of a chip-level interrupt, the major area of the device gene rating an interrupt is indicated in the lower 4 bits of the globcsr register. these bits are non-latching read-only status bits and do not need to be acknowledged. to acknowledge and clear a standing interrupt, the bit in lnkphyintack, itxintack, irxintack, or asyintack causing the interrup t status has to be written to a logic `1'; note: writing a value of `0' to the bit has no effect. 12.7.1 determining and clearing interrupts when responding to an interrupt event generated by the PDI1394L41, or operating in polled mode, the first register examined is the globcsr register. the least significant nibble contains interrupt status bits from general sections of the device; the link layer contr oller, the av transmitter, the av receiver, and the asynchronous transceiver. the bits in globcsr[3:0] are self clearing status bits. they represent the l ogical or of all the enabled interrupt status bits in their section of the av link layer controller. once an interrupt, or status is detected in globcsr, the appropriate interrupt status register needs to be read, see the interr upt hierarchy diagram for more detail. after all the interrupt indications are dealt with in the appropriate interrupt status register, the i nterrupt status indication will automatically clear in the globcsr. all interrupt status bits in the various interrupt status registers are latching unless otherwise noted.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 41 12.7.1.1 interrupt hierarchy 10 18 17 16 15 14 13 9 8 7 6 5 4 3 2 1 0 sv00913 76543210 3210 itxintack (0x02c) irxintack (0x04c) asyintack (0x0a0) lnkphyintack (0x008) globcsr (0x018) hif int_n phyint cmdrst fairgap phyrrx itbadfmt phyrst atbadfmt snt_rej hdrerr arbgap cystart tcerr cytmout cydone cypend cylost cysec inperr trmsyt trmbp discard itxfull itxempty dbcerr seqerr irxempty crcerr ciptagflt rcvbp fsync sqov asytx/rx itxint irxint lnkphyint 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 timeout rcvdrsp rrspqfull rreqqfull rreqqqav rrspqrderr rreqqrderr rrspqqav sidqav rreqqlastq trspqfull rrspqlastq treqqwrerr trspqwr trspqwrerr treqqfull treqqwr 6543210 irxfull 8 ir512lft 9 7 it512lft it256lft 8 ir256lft it100lft 9 20 timer 12 iremi 13 iro/e 21 auth dn 12 itemi 13 ito/e 10 ir100lft 14 m6 error figure 33. interrupt hierarchy 13.0 register map registers are 32 bits (quadlet) wide and all accesses are always done on a quadlet basis. this means that it is not possible to write just the lower 8 bits, and leave the other bits unaffected (see section 12.5.2 for more information). the values written to undefined fi elds/bits are ignored and thus don't care. a full bitmap of all registers is listed in table 6. the meaning of shading and bit cell values is as follows: a bit/field with no name written in it and dark shading is reserved and not used. a bit/field with a name in it and light shading is a read only (status) bit/field. a one bit value (0 or 1) written at the bottom of a writable (control) bit is the default value after power-on-reset. table 6. full bitmap of all registers (consists of four tables shown on the following pages)
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 42 0 it100lft 00 register address idreg 0x000 lnkctl 0x004 lnkphyinte 0x00c cyctm 0x010 phyacs 0x014 globcsr 0x018 itxpkctl 0x020 itxhq1 0x024 timer 0x01c 24 23 16 15 8 7 0 31 lnkphyintack 0x008 itxhq2 0x028 itxintack 0x02c itxinte 0x030 ediscard eitxfull eitxempty edbcerr einperr etrmbp etrmsyt discard itxfull itxempty dbcerr inperr trmbp trmsyt fmt fdf syt sph qpc fn dbs en_itx en_fs rst_itx pm trdel maxbl dirav1 asytx/rx itxint irxint lnkiphyint easytx/rx eitxint eirxint elnkphyint rdphy wrphy phyrgad phyrgdata phyrxad phyrxdata cycle_seconds cycle_number cycle_offset ecmdrst efairgap ehdrerr etcerr earbgap ephyint esnt_rej eitbadfmt eatbadfmt ephyrrx ecytmout ephyrst ecypend ecystart ecysec ecylost cmdrst fairgap hdrerr tcerr arbgap phyint snt_rej itbadfmt atbadfmt phyrrx cytmout phyrst cydone cypend cystart cysec cylost idvalid rcvselfid root busyflag cytmren strictisoch cymaster cysource rst tx rst rx txenable rxenable bsyctrl atack node id bus id 0000 000 000 00 00000 00 00 0000 000 0 0 00 00 01 0 00 0 0 0 0 0 00 0 0 0 0 0 00 0 0 000 00 00000 00 0 0 000 0 000000 00000 0 10000 0 00 0000 00000 00 0 0 000 0 0 0 00 0 00 00 000 0 00 00 0 00 00 00 00 0 0 0 0 0 0 00 0 0 00 00 00 0 0 0 0 0 0 00 0 00 00 00 000 0 00 00 0 1 1 01 version code sv01030 enoutav2 enoutav1 txap_clk 00 syt_delay 00 txrdy 0 it512lft 0 it256lft 0 eit256lft 0 eit512lft 0 1 0 part code ecydone 0 enxtmstp 0 timer 0 eit100lft 1 rpl 0 ltlend p datainv p 0 etimer 0 mlan 0 preload 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 tmbre 0 tmcont 0 tmgostop 0 auth dn 0 0 ito/e itemi 0 0 eito/e eitemi 0 eauth dn 0 m6 error 0 em6 error 0
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 43 register address itxctl 0x034 itxmem 0x038 irxpkctl 0x040 irxhq1 0x044 irxhq2 0x048 irxintack 0x04c irxinte 0x050 irxctl 0x054 irxmem 0x058 0x05c 0x07c sv01031 irxmaf irxm5av irxme irxmf tag channel err spd 00 0 0 000 0 eciptagflt ercvbp esqov ecrcerr eirxempty efsync eseqerr eirxfull 00 00 00 00 ciptagflt rcvbp sqov crcerr irxempty fsync seqerr irxfull 00 00 00 00 e1 f1 fmt syt fdf sph qpc fn dbs e0 f0 sid 24 23 16 15 8 7 0 31 en_fs rst_irx en_irx spav rmvuap bpad 0x03c . . . itxmaf itxm5av itxme itxmf tag channel spd 00 00 00 00 00 0 100001 rxap_clk 00 dis_tsc 0 ir512lft 0 ir256lft 0 eir256lft 0 eir512lft 0 sndimm 0 itxm512lft itxm256lft irxm512lft irxm256lft odd/even odd/even iro/e iremi eiro/e eiremi itxm100lft irxm100lft 0 0 0 0 0 emi 0 0 decphr_en sy 0 emi cphr_en ir100lft eir100lft 0 0 sy sytovf esytovf 0 0
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 44 etrspqfull etreqqwrerr etrspqwr etrspqwrerr etreqqfull etreqqwr errspqqav erreqqrderr erreqqlastq erreqqfull errspqfull etimeout erreqqqav errspqrderr esidqav errspqlastq timeout rcvdrsp rrspqfull rreqqfull rreqqqav rrspqrderr rreqqrderr rrspqqav sidqav rreqqlastq trspqfull rrspqlastq trspqwr trspqwrerr treqqfull treqqwr (write only) last quadlet of packet for transmitter request queue (write only) first/middle quadlet of packet for transmitter request queue trspqf trspqaf rrspqf rreqqe rreqqf rreqqaf rreqq5av rrspqaf rrspqe trspq5av rrspq5av treqqaf treqq5av treqqf trspqe treqqe arxall atxrst arxrst maxrc tos tof sv01032 (write only) last quadlet of packet for transmitter response queue (write only) first/middle quadlet of packet for transmitter response queue quadlet of packet from receiver request queue (transfer register) quadlet of packet from receiver response queue (transfer register) treqqwrerr 011000 00 000 00110 01 00000 0000 000 000 0 00000 0000 000 000 00 00000 register address asyctl 0x080 asymem 0x084 tx_rq_next 0x088 tx_rq_last 0x08c tx_rp_next 0x090 tx_rp_last 0x094 rreq 0x098 rrsp 0x09c asyintack 0x0a0 asyinte 0x0a4 0x0a8 0x0ac rdi 0x0b0 dis_bcast 0 trspqidle treqqidle ercvdrsp 0 31 24 23 16 15 8 7 0 epli 0 eloa 0 esca 0 esci 0 sci 0 sca 0 loa 0 pli 0 lpstat 0 swpd 0
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 45 sv01033 register address shadow_reg 0x0f4 31 24 23 16 15 8 7 0 byte 0 byte 1 byte 2 byte 3 indaddr 0x0f8 reserved indaddr inddata 0x0fc window to the indirect quadlet pointed to by indaddr 0 0 0011 1 1000 0101 0 0 000 0 10 10 000 00 00 0x0b4 . . . . 0x0f0
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 46 13.1 link control registers 13.1.1 id register (idreg) base address: 0x000 the id register is automatically updated by the attached phy with the proper node id after completion of the bus reset. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sv00915 node id bus id version code 3130 part code reset value 0xffff1001 bit 31..22: r/w bus id: the 10-bit bus number that is used with the node id in the source address for outgoing packets and used to accept or reject incoming packets. this field reverts to all `1's (0x3ff) upon bus reset. bit 21..16: r/w node id: used in conjunction with bus id in the source address for outgoing packets and used to accept or reject incoming packets. this register auto-updates with the node id assigned after the 1394 bus tree-id sequence. bit 15..8: r part code: a02o designates PDI1394L41. bit 7..0: r version code: a01o shows this is revision level 1 of this part. 13.1.2 general link control (lnkctl) base address: 0x004 the general link control register is used to program the link layer isochronous transceiver, as well as the overall link transc eiver. it also provides general link status. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sv00892 idvalid rcvselfid root busyflag cytmren strictisoch cymaster cysource rst tx rst rx txenable rxenable bsyctrl atack 31 30 txrdy rpl datainv ltlend reset value 0x46000002 bit 31: r/w idvalid (idvalid): when equal to one, the PDI1394L41 accepts the packets addressed to this node. this bit is automatically set after selfid complete and node id is updated. bit 30: r/w receive self id (rcvselfid): when asserted, the self-identification packets, generated by each phy device on the bus, during bus initialization are received and placed into the asynchronous request queue as a single packet. bit 30 also enables the reception of phy configuration packets in the asynchronous request queue. bit 29..27: r/w busy control (bsyctrl): these bits control what busy status the chip returns to incoming packets. the field is defined below: 000 = use protocol requested by received packet (either dual phase or single phase) 001 = reserved 010 = reserved 011 = use single phase retry protocol 100 = use protocol requested in packet, always send a busy ack (for all packets) 101 = reserved 110 = reserved 111 = use single phase retry protocol, always send a busy ack bit 26: r/w transmitter enable (txenable): when this bit is set, the link layer transmitter will arbitrate and send packets. bit 25: r/w receiver enable (rxenable): when this bit is set, the link layer receiver will receive and respond to bus packets. bit 23: r data invariant (datainv) refers to the byte ordering of data being presented to the link through the host interface (hif) port and the handling of the address and data lines by the link chip. when datainv = 0, the link is in address invariant mode. when datainv = 1, the link is in data invariant mode. this bit is only important if the ltlend (little endian) bit is set (1), otherwise it is ignored. interpretation of address and data information varies with the settings of these bits and with the data format being presented. see the section on big and little endian modes for more information (section 12.5.3).
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 47 bit 22: r little endian (ltlend): refers to the state of the endianess of the data and address lines connected to the 'l41. this bit reflects the state of the av2err0/ltlend pin during power reset. the state of this pin is read during reset and that state is latched into this bit position. when ltlend = 0, the chip is set to receive big endian address and data on its host interface (hif). when ltlend = 1, the link chip will receive little endian oriented data and address information. if this bit is set (1), the state of the datainv pin will also become important for determination of data positions in the internal link registers. see the section on big and little endian modes for more information (section 12.5.3). bit 21: r/w reset transmitter (rsttx): when set to one, this synchronously resets the transmitter within the link layer. bit 20: r/w reset receiver (rstrx): when set to one, this synchronously resets the receiver within the link layer. bit 18: r/w reset phy-link interface (rpl): resets the phylink interface in accordance with 1394a requirements. note: this bit automatically resets to a0o when the interface reset operation has been completed. the phylink reset operation occurs very quickly, reading this bit accurately is not usually possible. before asserting the rpl bit, swpd or setting the pd pin high, the user should assure that the link chip is in the following state of operation: 1) the isochronous transmit fifo is not receiving data for transmission 2) the isochronous transmitter is disabled 3) no asynchronous packets are being generated for transmission 4) both the async request and response queues are empty bit 12: r/w strict isochronous (strictisoch): used to accept or reject isochronous packets sent outside of specified isochronous cycles (between a cycle start and subaction gap). a `1' rejects packets sent outside the specified cycles, a a0o accepts isochronous packets sent outside the specified cycle. bit 11: r/w cycle master (cymaster): when asserted and the PDI1394L41 is attached to the root phy (root bit = 1), and the cycle_count field of the cycle timer register increments, the transmitter sends a cycle-start packet. cycle master function will be disabled if a cycle timeout is detected (cytmout bit 5 in lnkphyintack). to restart the cycle master function in such a case, first reset cymaster, then set it again. bit 10: r/w cycle source (cys ource): when asserted, the cycle_count field increments and the cycle_offset field resets for each positive transition of cyclein. when deasserted, the cycle count field increments when the cycle_offset field rolls over. bit 9: r/w cycle timer enable (cytimren): when asserted, the cycle offset field increments. when deasserted, the cycle timer register (0x010, cyctm) can be used as a general read write register for host interface firmware testing. bit 6: r transmitter ready (txrdy): the transmitter is idle and ready. bit 5: r root (root): indicates this device is the root on the bus. this automatically updates after the self_id phase. bit 4: r busy flag (busyflag): the type of busy acknowledge which will be sent next time an acknowledge is required. 0 = busy a, 1 = busy b (only meaningful during a dual-phase busy/retry operation). bit 3..0: r at acknowledge received (atack): the last acknowledge received by the transmitter in response to a packet sent from the transmit-fifo interface while the atf is selected (diagnostic purposes).
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 48 13.1.3 link /phy interrupt acknowledge (lnkphyintack) base address: 0x008 the link/phy interrupt acknowledge register indicates various status and error conditions in the link and phy which can be prog rammed to generate an interrupt. the interrupt enable register (lnkphyinte) is a mirror of this register. acknowledgment of an interrupt is accomplished by writing a `1' to a bit in this register that is set. this action reset the bit indication to a `0'. writing a `1' to a bit t hat is already a0o will have no effect on the register. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sv01040 cmdrst fairgap hdrerr tcerr arbgap phyint snt_rej itbadfmt atbadfmt phyrrx cytmout phyrst cydone cypend cystart cysec cylost 31 30 timer auth dn reset value 0x00000000 bit 21: r/w authentication acceleration done (auth dn). the authentication accelerator has finished an operation. check the status of `valid' in the authentication accelerator indirect register. bit 20: r/w timer (timer): when timer = 1, this bit indicates that the timer has counted down to zero. this interrupt may occur only once or may occur repeatedly, according to the setting of the tmcont bit in the timer register. acknowledge this interrupt by writing a a1o back into this bit position. bit 18: r/w command reset received (cmdrst): a write request to reset-start has been received. bit 17: r/w fair gap (fairgap): the serial bus has been idle for a fair-gap time (called subaction gap in the ieee 1394 specification). bit 16: r/w arbitration reset gap (arbgap): the serial bus has been idle for an arbitration reset gap. bit 15: r/w phy chip int (phyint): the phy chip has signaled an interrupt through the phy interface after a bus reset or phy reset. this bit becomes active for any of the following reasons (1) phy has detected a loop on the bus, (2) cable power has fallen below the minimum voltage, (3) the phy arbitration state machine has timed-out usually indicative of a bus loop, (4) a bus cable has been disconnected. typically, recognition and notification of any of the above events by the phy requires between 166 and 500 microseconds; therefore, this bit is not instantaneously set. bit 14: r/w phy register information received (phyrrx): a register has been transferred by the physical layer device into the link. bit 13: r/w phy reset started (phyrst): a phy-layer reconfiguration has started. this interrupt clears the id valid bit. (called bus reset in the ieee 1394 specification). the async queues will be flushed during a bus reset. bit 10: r/w isochronous transmitter is stuck (itbadfmt): the transmitter has detected invalid data at the transmit-fifo interface when the itf is selected. reset the isochronous transmitter to clear. bit 9: r/w asynchronous transmitter is stuck (atbadfmt): the transmitter expected start of new async packet in queue, but found other data (out of sync with user). reset the asynchronous transmitter to clear. bit 8: r/w busy acknowledge sent by receiver (snt_rej): the receiver was forced to send a busy acknowledge to a packet addressed to this node because the receiver response/request fifo overflowed. bit 7: r/w header error (hdrerr): the receiver detected a header crc error on an incoming packet that may have been addressed to this node. bit 6: r/w transaction code error (tcerr): the transmitter detected an invalid transaction code in the data at the transmit fifo interface. bit 5: r/w cycle timed out (cytmout): isoch cycle lasted more than 125 m s from cycle-start to fair gap: disables cycle master function bit 4: r/w cycle second incremented (cysec): the cycle second field in the cycle-timer register incremented. this occurs approximately every second when the cycle timer is enabled. bit 3: r/w cycle started (cystart): the transmitter has sent or the receiver has received a cycle start packet. bit 2: r/w cycle done (cydone): a fair gap has been detected on the bus after the transmission or reception of a cycle start packet. this indicates that the isochronous cycle is over; note: writing a value of `0' to the bit has no effect. bit 1: r/w cycle pending (cypend): cycle pending is asserted when cycle timer offset is set to zero (rolled over or reset) and stays asserted until the isochronous cycle has ended. bit 0: r/w cycle lost (cylost): the cycle timer has rolled over twice without the reception of a cycle start packet. this only occurs when cycle master is not asserted.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 49 13.1.4 link / phy interrupt enable (lnkphyinte) base address: 0x00c this register is a mirror of the link/phy interrupt acknowledge (lnkphyintack) register. enabling an interrupt is accomplished by writing a `1' to the bit corresponding to the interrupt desired. this register enables the interrupts described in the link /phy interrupt acknowledge register (lnkphyintack) description. a on e in any of the bits enables that function to create an interrupt. a zero disables the interrupt, however the status is readable in the link /p hy interrupt acknowledge register. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ecmdrst efairgap ehdrerr etcerr earbgap ephyint esnt_rej eitbadfmt eatbadfmt ephyrrx ecytmout ephyrst ecydone ecypend ecystart ecysec ecylost sv00894 31 30 etimer eauth dn reset value 0x00000000 bits 21..0 are interrupt enable bits for the link/phy interrupt acknowledge (lnkphyintack). 13.1.5 cycle timer register (cyctm) base address: 0x010 cycle timer register operation is controlled by the cycle timer enable (cytmren) bit in the link control register (lnkctl, 0x00 4). if the cycle timer register is disabled, it can be used as a general read write register for host interface firmware testing. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cycle_seconds cycle_number cycle_offset sv00276 3130 reset value 0x00000000 bit 31..25: r/w seconds count: 1-hz cycle timer counter. bit 24..12: r/w cycle number: 8khz cycle timer counter. bit 11..0: r/w cycle offset: 24.576mhz cycle timer counter.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 50 13.1.6 phy register access (phyacs) base address: 0x014 this register provides access to the internal registers on the phy. there are special considerations when reading or writing to this register. when reading a phy register, the address of the register is written to the phyrgad field with the rdphy bit set. the phy data will b e valid when the phyrrx bit (lnkphyintack register bit 14) is set. once this happens the register data is available in the phyrxdata, the addres s of the register just read is also available in the phyrxad fields. when writing a phy register, the address of the register to be writ ten is set in the phyrgad field and the data to be written to the register is set in phyrgdata, along with the wrphy bit being set. once the writ e is complete, the wrphy bit will be cleared. do not write a new read/write command until the previous one has been completed. after the self-id phase, phy register 0 will be read automatically. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rdphy wrphy sv00277 phyrgad phyrgdata phyrxad phyrxdata 31 30 reset value 0x00000000 bit 31: r/w read phy chip register (rdphy): when asserted, the PDI1394L41 sends a read register request with address equal to phy rg ad to the phy interface. this bit is cleared when the request is sent. bit 30: r/w write phy chip register (wrphy): when asserted, the PDI1394L41 sends a write register request with address equal to phy rg ad to the phy interface. this bit is cleared when the request is sent. bit 27..24: r/w phy chip register address (phyrgad): this is the address of the phy-chip register that is to be accessed. bit 23..16: r/w phy chip register data (phyrgdata): this is the data to be written to the phy-chip register indicated in phy rg a d. bit 11..8: r phy chip register received address (phyrxad): address of register from which phy rx data came. bit 7..0: r phy chip register received data (phyrxdata): data from register addressed by phy rx ad. 13.1.7 global interrupt status and tx control (globcsr) base address: 0x018 this register is the top level interrupt status register. if the external interrupt line is set, this register will indicate wh ich major portion of the av link generated the interrupt. there is no interrupt acknowledge required at this level. these bits auto clear when the interrup ts in the appropriate section of the device are cleared or disabled. control of the av transceiver is also provided by this register. bits 0 to 3 are used to identify which internal modules are currently generating an interrupt. after identifying the module, th e appropriate register in that module must be read to determine the exact cause of the interrupt. a timer is available to aid the implementation of higher level protocols such as av/c and havi. the timer can be started and st opped, and automatically reloads with 1s (timload = 1) or 100ms (timload = 0). when the set time has expired, an interrupt will be generat ed through timer (bit 20, lnkphyintack 0x008). in normal timer mode (timmode = 0), the timer will generate an interrupt, reload and restar t every time it expires, until timrnstp is cleared. in bus reset timer mode (timmode = 1), even when already running the timer will rel oad with 1s and restart automatically after a bus reset. if another bus reset occurs before the timer expires, the timer will again reload and restart. no interrupt will be generated until the timer expires. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 asytx/rx itxint irxint lnkphyint 31 30 easytx/rx eitxint eirxint elnkphyint dirav1 enoutav2 enoutav1 sv01024 notes 1. there can be more than one interrupt source active at the same time. 2. the hif int_n signal (pin 28) remains active as long as there is at least one more enabled active interrupt status bit. reset value 0x00010000 bit 18: r/w enable output avport2: a `1' enables avport2 as an output. a `0' sets the 3-state condition on the port. in 3-state condition the port may be used as an input or unused output according to the state of dirav1 (bit 16). bit 17: r/w enable output avport1: a `1' enables avport1 as an output. a `0' sets the 3-state condition on the port. in 3-state condition the port may be used as an input or unused output according to the state of dirav1 (bit 16).
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 51 bit 16: r/w direction of avport1 (dirav1): a `1' enables avport1 as a transmitter, thus avport1 pins are inputs. a `0' configures avport1 as a receiver, avport1 pins are outputs in this configuration. the configuration of avport2 pins is opposite of avport1 pins. when avport1 is set to transmit, avport2 receives and vice versa. bit 11: r/w enables generation of external interrupt by asynchronous transmitter and receiver module (asytx/rx, bit 3) when set (1). disables such interrupts when clear (0) (regardless of asyinte contents). bit 10: r/w enables generation of external interrupt by the isochronous transmitter module (itxint, bit 2) when set (1). disables such interrupts when clear (0) (regardless of itxinte contents). bit 9: r/w enables generation of external interrupt by the isochronous receiver module (irxint, bit 1) when set (1). disables such interrupts when clear (0) (regardless of irxinte contents). bit 8: r/w enables generation of external interrupt by general link/phy module (lkphyint, bit 0) when set (1). disables such interrupts when clear (0) (regardless of lnkphyinte contents). bit 3: r asynchronous transmitter/receiver interrupt (asyitx/rx): interrupt source is in the asynchronous transmitter/ receiver interrupt acknowledge/source register. bit 2: r av transmitter interrupt (itxint): interrupt source is in the av transmitter interrupt acknowledge/source register. bit 1: r av receiver interrupt (irxint): interrupt source is in the av receiver interrupt acknowledge/source register. bit 0: r link-phy interrupt (lnkphyint): interrupt source is in the link phy interrupt acknowledge register. 13.1.8 timer (timer) base address: 0x01c preload 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sv01096 31 30 tmgostop tmcont tmbre reset value bit 31: r/w tmgostop: timer go/stop, when = 1 start timer; when = 0 stop timer. bit 30: r/w tmcont: timer continuous, when = 1 continuously operate timer; when = 0 operate timer for one timing cycle, then stop. bit 29: r/w tmbre: timer bus reset enable, when = 1, start the timer at the beginning of a bus reset; when = 0 start the timer from the tmgostop bit setting. bit 23..0: r/w timer preload bits. load a number into the timer preload bits with the most significant bit in the higher numbered bit position; the least significant bit in the timer preload register is bit 0. the basic timing unit is 1/(2*clk25) or 80.14 nanoseconds. the maximum timer time-out is about 1.34 seconds ((2^24)1 units). the timer uses the preload value inputted by the host into bits 0 through 23 of this register. the preload value is placed in the actual timer/counter (invisible to outside world) and this value is decremented by 1 for each unit of time. the timer eventually counts down to zero and then it sets the timer interrupt flag bit in register 0x008, linkphyintack (assuming the interrupt was enabled by the etimer bit). depending on the setting of the tmcont bit in this register, the timer preload value may be automatically reloaded into the timer/counter (when tmcont = 1) with the timing cycle automatically re-starting, or the timer will simply interrupt and stop (when tmcont bit = 0). tmbre adds a mode to the timer operation which starts the timing automatically at the start of a 1394 bus reset. when tmbre is set (1), the tmgostop bit function is disabled; the tmcont bit function is still available. note: when tmcont = 1, failing to acknowledge a timer interrupt has no effect on the starting/restarting of the timer; if an interrupt is not acknowledged (bit reset), the timer will continue to time out and restart.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 52 13.2 av (isochronous) transmitter and receiver registers 13.2.1 isochronous transmit packing control and status (itxpkctl) base address: 0x020 this register allows the user to set up the appropriate av packets from data entered into the av interface. the packing and con trol parameters (trdel, maxbl, dbs, fn, qpc, and sph) should never be changed while the transmitter is operating. the only exception to this is the maxbl parameter when in mpeg-2 packing mode. note: when reset of isochronous transmitter is necessary, first disable the transmitter (place bit 4, en_itx, low), wait for fi fo to empty, then reset the transmitter (place rst_itx, bit 0, high). this procedure will ensure that data in the fifo is transmitted before rese t. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 en_itx en_fs rst_itx sv00886 pm trdel maxbl 31 30 txap_clk syt_delay enxtmstp mlan reset value 0x00000001 bit 30: r/w mlan mode bit: when = 1, syt system is in mlan mode. when mlan = 0 normal syt time stamping operation is assumed. with mlan = 1, the syt time stamp for an fsync pulse will not be appended to an empty bus packet. any pending syt stamp will be held until the next non-empty bus packet is sent. as an fsync pulse is input to the transmitting node's link chip, an syt stamp will be made. this syt stamp will point to a time in the future dictated by the syt delay value (in register 0x020) added to the current least significant nibble (lsn) of the cycle number, plus the current cycle offset value. this mode automatically increases syt_delay value by two additional cycles beyond the value programmed in the syt_delay bits. bit 29..28: r/w txap_clk: application clock, default mode, `00' the avxclk pin is an input. this pin can become an application clock for the isochronous transmitter (and output) by programming it to `01', `10', or `11'. the programming values are: 00 input 01 24.576mhz 10 12.288mhz 11 6.144mhz note that when enabled as `01', `10', or `11', the av port that is configured as transmitter and enabled will output this clock signal on its avxclk pin. bit 27..16: r/w trdel: transport delay. value added to cycle timer to produce time stamps. lower 4 bits add to upper 4 bits of cycle_offset, (cycle timer register, cyctm). remainder adds to cycle_count field. bit 15..8: r/w maxbl: the (maximum) number of data blocks to be put in a payload. bit 7: r/w enxtmstp: enable external time stamp control. allows an external time stamp (generated by the application) to be inserted in place of the link-generated time stamp. defaults to link generated time stamp. the application must present the first byte of a quadlet-wide time stamp accompanied by the avsync pulse (and avvalid) to the avport. the external time stamp quadlet is inputted first, followed by the application data packet. the transmitted packet size is now one quadlet larger than the original isochronous data packeteset up the isochronous transmitter accordingly with sph = 1. caution : unless valid iec 61883 time stamp format (based on the link cycle timer) is used, the receiving node link chip must be equipped with a time stamp check disabling function similar to the dis_tsc bit (register 0x040, bit 7). please see section 13.2.8 for details. bit 6..5: r/w syt_delay: programmable delay of av1fsync and av2fsync. each cycle is 1 bus cycle, 125 s. reset value is a00o, a 3 cycle delay. 01 = 2 cycles 00 = 3 cycles 10 = 4 cycles 11 = reserved bit 4: r/w en_itx: enable receipt of new application packets and generation of isochronous bus packets in every cycle. this bit also enables the link layer to arbitrate for the transmitter in each subsequent bus cycle. when this bit is disabled (0), the current packet will be transmitted and then the transmitter will shut down. bit 3..2: r/w pm: packing mode: 00 = variable sized bus packets, most generic mode. 01 = fixed size bus packets. 10 = mpeg2 packing mode. 11 = no data, just cip headers are transmitted. bit 1: r/w en_fs:enable generation/insertion of syt stamps (time stamps) in cip header. bit 0: r/w reset isochronous transmitter (rst_itx): causes transmitter to be reset when `1'. in order for synchronous reset of itx to work properly, an avxclk (from either the internal or external source) must be present and ensure that the reset bit is kept (programmed) high for at least the duration of one avxclk period. failure to do so may cause the application interface of this module to be improperly reset (or not reset at all). when reset is enabled, all bytes will be flushed from the fifo and transmission will cease immediately.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 53 13.2.2 common isochronous transmit packet header quadlet 1 (itxhq1) base address: 0x024 the av transmit packing control register holds the specification for the packing scheme used on the av data stream. this inform ation is included in common isochronous packet (cip) header quadlet 1. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sph qpc fn dbs sv01747 31 30 reset value 0x00000000 bit 16..23: r/w dbs: size of the data blocks from which av payload is constructed. the value 0 represents a length of 256 quadlet s. bit 14..15: r/w fn: (fraction number) the encoding for the number of data blocks into which each source packet shall be divided (00 = 1, 01 = 2, 10 = 4, 11 = 8). bit 11..13: r/w qpc: number of dummy quadlets to append to each source packet before it is divided into data blocks of the specified size. the value qpc must be less than dbs and less than 2 fn . bit 10: r/w sph: indicates that a 25-bit cyctm based time stamp has to be inserted before each application packet. 13.2.3 common isochronous transmit packet header quadlet 2 (itxhq2) base address: 0x028 the contents of this register are copied to the second quadlet of the cip header and transmitted with each isochronous packet. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fmt fdf sv00281 31 30 syt reset value 0x00000000 bit 29..24: r/w fmt: value to be inserted in the fmt field in the av header. bit 23..0: r/w fdf/syt: value to be inserted in the fdf field. when the en_fs bit in the transmit control and status register (itxpkctl) is set (=1), the lower 16 bits of this register are replaced by an syt stamp if a rising edge on avfsyncin has been detected or all `1's if no such edge was detected since the previous packet. the upper 8 bits of the register are sent as they appear in the fdf register. when the en_fs bit in the transmit control and status register is unset (=0), the full 24 bits can be set to any application specified value.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 54 13.2.4 isochronous transmitter interrupt acknowledge (itxintack) base address: 0x02c the av transmitter interrupt control and status register is the interrupt register for the av transmitter. bits 2, 3, and 4 aauto repairo themselves, i.e. avlink will detect the situation and attempt to recover on its own. the host co ntroller still needs to clear these interrupts to be alerted the next time. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 discard itxfull itxempty dbcerr inperr trmbp trmsyt pldsci itxmfi itxmei dbcei iddsci eoti sytti sv01054 31 30 it512lft it256lft it100lft itemi ito/e m6 error reset value 0x00000000 bit 14: r/w m6 error: either the m6 cipher block has encountered an unrecoverable error. proper operation will be resumed by disabling and resetting the itx. bit 13: r/w ito/e: an odd/even key change has occurred in the cipher, it is now ok to write in the new key set. bit 12: r/w itemi: this bit indicates that the emi bit value used to cipher outgoing transmission has changed. bits 9 .. 0 are interrupt acknowledge bits; and are defined as: bit 9: r/w it100lft: interrupt when transmitter queue reaches 100 quadlets from full. bit 8: r/w it256lft: interrupt when transmitter queue reaches 256 quadlets from full. bit 7: r/w it512lft: interrupt when transmitter queue reaches 512 quadlets from full. this bit is disabled if 0.5k byte buffer size is set. bit 6: r/w trmsyt: interrupt on transmission of a syt in cip header quadlet 2 bit 5: r/w trmbp: interrupt on payload transmission/discard complete. bit 4: r/w dbcerr: acknowledge interrupt on data block count (dbc) synchronization loss. bit 3: r/w inperr: acknowledge interrupt on input error (input data discarded). bit 2: r/w discard: interrupt on lost cycle (payload discarded). bit 1: r/w itxfull: interrupt on isochronous memory bank full. this is a fatal error. the itx transmitter will reset itself automatically when this occurs. bit 0: r/w itxempty: interrupt on isochronous memory bank empty. other bits will always read `0'. 13.2.5 isochronous transmitter interrupt enable (itxinte) base address: 0x030 these are the enabled bits for the av transmitter control. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ediscard eitxfull eitxempty edbcerr einperr etrmbp etrmsyt pldsci itxmfi itxmei dbcei iddsci eoti sytti 31 30 sv01055 eit512lft eit256lft eit100lft eitemi eito/e em6 error reset value 0x00000000 bits 13..0 are interrupt enable bits for the isochronous transmitter interrupt acknowledge register (itxintack).
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 55 13.2.6 isochronous transmitter control register (itxctl) base address: 0x34 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sv01016 tag channel spd 31 30 odd/even cphr_en sy emi reset value 0x00000000 bit 20: r/w cipher enable: when set, the internal m6 cipher will encrypt the application packets with the associated key in the m6 indirect address space for the given emi value assigned. when the emi value changes the cipher will automatically change the key on the next application packet. writes to the odd/even bit (bit 1 will automatically swap the odd/even key in the cipher. note: the maximum average data rate for the m6 cipher is 60 mbps. bit 15..14: r/w tag: tag code to insert in isochronous bus packet header. should be `01' for iec 61883 international standard d ata. bit 13..8: r/w channel: isochronous channel number. bit 5..4: r/w speed: cable transmission speed (s100, s200, s400). 00 = 100mbs 01 = 200mbs 10 = 400mbs 11 = reserved bit 3..2 r/w encryption mode indication: this bit pattern specifies the level of copy control information for the data stream. th e field only has significance when the internal cipher is enabled (cphr_en = 1). the bits are read only and follow the value of the avxemi pins when emi_pe = 1 (bit 19). the bits are read/write when emi_pe = 0. see the a5c digital transmission content protections specification, volume 1o for more details about emi values. bit 1 r/w odd even bit used for encryption key (0 = even, 1 = odd). when the internal m6 cipher is enabled (cphr_en = 1), a write that changes this bit field will cause the cipher to swap its odd/even key. the key will be changed on the very next application packet and an interrupt (oddevn) will be generated. see the a5c digital transmission content protection specification, volume 1o for more details about odd/even values. when the internal cipher is not enabled (cphr_en = 0) the bit value is r/w and the current bit value will be transmitted in the isochronous header. bit 0 r sy: sync code to insert in sy field of isochronous bus packet header. this bit reflects the value of the avx sy pin and is synchronized with the data payload that was associated with it. 13.2.7 isochronous transmitter memory status (itxmem) base address: 0x038 the av transmitter memory status register reports on the condition of the internal memory buffer used to store incoming av data streams before transmission over the 1394 bus. this register is used primarily for diagnostics; several memory status flags are also av ailable in the itxintack register. itxm512lft itxm256lft itxm100lft 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 itxmaf itxm5av itxme itxmf sv01056 3130 reset value 0x00000003 bit 6: r itxm100lft: 100 or less quadlets of storage available. bit 5: r itxm256lft: memory has 256 quadlets of space remaining before becoming full. bit 4: r itxm512lft: memory has 512 quadlets of space remaining before becoming full. bit 3: r itxmf: memory is completely full, no storage available. bit 2: r itxmaf: almost full, exactly one quadlet of storage available. bit 1: r itxm5av: at least 5 more quadlets of storage available. bit 0: r itxme: memory bank is empty (zero quadlets stored).
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 56 13.2.8 isochronous receiver unpacking control (irxpkctl) base address: 0x040 note: when receiver reset is required, first disable receiver (en_irx = 0), then wait until rx fifo is emptied, then perform th e reset. this will allow previously received packets to go to the application instead of being lost. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 en_fs rst_irx en_irx spav rmvuap sv00887 bpad 31 30 rxap_clk dis_tsc sndimm reset value 0x00000041 av receiver control bits. bit 29..28: r/w rxap_clk: receiver application clock, default mode, `00' the avxclk pin is an input. this pin can become an application clock and output for the isochronous receiver by programming it to `01', `10', or `11'. the programming values are: 00 input 01 24.576mhz 10 12.288mhz 11 6.144mhz note that when enabled as `01', `10', or `11', the av port that is configured as receiver and enabled will output this clock signal on its avxclk pin. bit 8: r/w sndimm: send immediately; when set to a1o, this bit will allow a received isochronous packet containing a crc error to be output immediately (without regard to the time stamp value). this bit defaults to a0o. in default (reset) mode, the packet will be output with respect to the time stamp value, even if there is a crc error. caution: if there is an error in the time stamp, the packet may be held far into the future. this will affect subsequently received packets. bit 7: r/w dis_tsc: disable time stamp checking. defaults to a0o, time stamp checking is enabled. when time stamp checking is disabled, the time stamp accompanying a packet is output before the packet to the application for use by the application. this adds an extra quadlet of data to the received data stream; the application must be capable of handling this extra 4 bytes. bit 6: r/w rmvuap: remove unreliable packets from memory, do not attempt delivery bit 5: r spav: source packet available for delivery in buffer memory. bit 4: r/w en_irx: enable receiver operation. value is only checked whenever a new bus packet arrives, so enable/disable while running is `graceful', meaning any transfers in process will be completed before this bit is asserted. bit 2..3: r/w bpad: value indicating the amount of byte padding to be removed from the last data quadlet of each source packet, from 0 to 3 bytes. this is in addition to quadlet padding as defined in iec 61883 international standard. bit 1: r/w en_fs: enable processing of syt stamps. bit 0: r/w rst_irx: causes the receiver to be reset when `1'. in order for synchronous reset of irx to work properly, the application must supply an avclk and ensure that the reset bit is kept (programmed) high for at least the duration of one avclk period. failure to do so may cause the application interface of this module to be improperly reset (or not reset at all).
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 57 13.2.9 common isochronous receiver packet header quadlet 1 (irxhq1) base address: 0x044 this quadlet represents the last received header value when av receiver is operating. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sph qpc fn dbs sv00286 e0 f0 31 30 sid reset value 0x00000000 bit 31..30: r e0: end of header, f0: format: always set to 00 for first av header quadlet. bit 29..24 r sid: source id, contains the node address of the sender of the isochronous data. bit 23.16: r dbs: size of the data blocks from which av payload is constructed. the value 0 represents a l ength of 256 quadlets. bit 15..14: r fn (fraction number): the encoding for the number of data blocks into which each source packet has been divided (00 = 1, 01 = 2, 10 = 4, 11 = 8) by the transmitter of the packet. bit 13..11: r qpc: number of dummy quadlets appended to each source packet before it was divided into data blocks of the specified size. bit 10: r sph: indicates that a cyctm based time stamp is inserted before each application packet (25 bits specified in the iec 61883 international standard). 13.2.10 common isochronous receiver packet header quadlet 2 (irxhq2) base address: 0x048 e1 f1 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 fmt syt sv00287 31 30 fdf reset value 0x0000ffff bit 31..30: r e1: end of header, f1: format: should be set to 10 for second av header quadlet. bit 29..24: r fmt: value inserted in the format field. bit 23..0: r fdf/syt: if ``en fso in register irxpkctl (0x040) is set to `1', then lower 16-bits are interpreted as syt.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 58 13.2.11 isochronous receiver interrupt acknowledge (irxintack) base address: 0x04c 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ciptagflt rcvbp sqov crcerr irxempty fsync seqerr ir512lft sv01025 31 30 ir256lft ir100lft iro/e iremi irxfull sytovf reset value 0x00000000 bit 14: r/w sytovf: syt fifo overflow. the isochronous receiver's syt field fifo has overflowed and has been automatically reset and cleared. this interrupt alerts the host controller that up to 7 avfsync pulses may be missing due to an syt field reception error. bit 13: r/w iro/e: odd/even key change. software should write in the new set of keys to the cipher. bit 12: r/w iremi: this bit indicates when there has been a change in the received emi bit values (bits 2 and 3 of register 0x054). this interrupt, when = 1, indicates that a changed emi field has been received. bit 10: r/w ir100lft: interrupt when receiver queue reaches 100 quadlets from full. bit 9: r/w ir256lft: interrupt when receiver queue reaches 256 quadlets from full. bit 8: r/w ir512lft: interrupt when receiver queue reaches 512 quadlets from full. this bit is disabled if 0.5k byte buffer siz e is set. bit 7: r/w irxfull: isochronous data memory bank has become full. this is a fatal error, the recommended action is to reset and re-initialize the receiver. bit 6: r/w irxempty: isochronous data memory bank has become empty. bit 5: r/w fsync: pulse at fsync output. bit 4: r/w seqerr: sequence error of data blocks. bit 3: r/w crcerr: crc error in bus packet. bit 2: r/w ciptagflt: faulty cip header tag (e,f bits). i.e.: the cip header did not meet the standard and the whole packet is ignored. bit 1: r/w rcvbp: bus packet processing complete. bit 0: r/w sqov: status queue overflow. this is a fatal error, the recommended action is to reset and re-initialize the receiver. 13.2.12 isochronous receiver interrupt enable (irxinte) base address: 0x050 interrupt enable bits for av receiver. 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 eciptagflt ercvbp esqov ecrcerr eirxempty efsync eseqerr eir512lft 31 30 sv01026 eir256lft eir100lft eiro/e eiremi eirxfull esytovf reset value 0x00000000 bit 13..0 are interrupt enable bits for the isochronous receiver interrupt acknowledge (irxintack).
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 59 13.2.13 isochronous receiver control register (irxctl) base address: 0x054 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tag channel err sv01041 spd 31 30 odd/even emi decphr_en sy reset value 0x00000000 bit 20: r/w de-cipher enable: when set the internal m6 cipher will decrypt the application packets with the associated key in the m6 indirect address space for the given emi value assigned. when the emi value changes, the cipher will automatically change the key on the next application packet. changes to the odd/even bit (bit 1) will automatically swap the odd/even key in the cipher. note: the maximum average data rate for the m6 cipher is 60 mbps. bit 17..16: r spd: speed of last received isochronous packet (s100 .. s400). 00 = 100 mbps 01 = 200 mbps 10 = 400 mbps 11 = reserved bit 15..14: r/w tag: isochronous tag value (must match) for av format, `01' for iec 61883 international standard data. bit 13..8: r/w chan: channel number to receive isochronous data. bit 7..4: r err: error code for last received isochronous av packet. bit 3..2: r encryption mode indication: this bit pattern specifies the level of copy control information for the data stream. the field only has significance when the internal cipher is enabled (decphr_en = 1). the value of these bits is stored and accompanies the received packet through the irx fifo. at a later time, when the first byte of the accompanied packet is presented at the receiving av port, that emi value is also presented. note: the emi value in this register is indicative only of the emi value of the packet which is being received from the bus. the emi value at the av port may differ due to aging as it progresses through the irx fifo. see the a5c digital transmission content protection specification, volume 1o for more details about emi values. bit 1: r odd/even: used for encryption key (0= even, 1 = odd). when the internal m6 decipher is enabled (decphr_en = 1), changes to this bit field will cause the cipher to swap its odd/even key. an interrupt will be generated, `odd/even' in the irxintack register to allow firmware to update key sets. see the a5c digital transmission content protection specification, volume 1o for more details about odd/even values. bit 0: r sy: sync code to insert in sy field of isochronous bus packet header. this bit reflects the value of the sy bit received from the isochronous header and is synchronized in the receiver fifo with the data payload that was associated with it. note: the sy value in this register is indicative only of the emi packet which is being received from the bus. the sy value at the av port may differ due to aging as it progresses through the irx fifo. table 7. error codes code name meaning 0000 reserved 0001 ack_complete the node has successfully accepted the packet. if the packet was a request subaction, the destination node has successfully completed the transaction and no response subaction shall follow. 0010 through 1100 reserved 1101 ack_data_error the node could not accept the block packet because the data field failed the crc check, or because the length of the data block payload did not match the length contained in the datalength field. this code shall not be returned for any packet that does not have a data block payload. 1110 and 1111 reserved
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 60 13.2.14 isochronous receiver memory status (irxmem) base address: 0x058 the av receiver memory status register reports on the condition of the internal memory buffer used to store outgoing av data st reams after reception from the 1394 bus. this register is used primarily for diagnostics; several memory flags are also available in the ir xintack register. irxmaf irxm5av irxme irxmf irxm512lft irxm256lft irxm100lft 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sv01057 31 30 reset value 0x00000003 bit 6: r irxm100lft: fifo is 100 quadlets from full. bit 5: r irxm256lft: fifo is 256 quadlets from full. bit 4: r irxm512lft: fifo is 512 quadlets from full. bit 3: r irxmf: full: no space available. bit 2: r irxmaf: almost full: exactly one quadlet of storage available. bit 1: r irxm5av: at least 5 more quadlets of storage available. bit 0: r rxme: memory bank is empty (no data committed).
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 61 13.3 asynchronous control and status interface 13.3.1 asynchronous rx/tx control (asyctl) base address: 0x080 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 arxall atxrst arxrst sv00889 maxrc tos tof 31 30 dis_bcast reset value 0x00300320 bit 23: r/w dis_bcast: disable the reception of broadcast packets (async packets address to 0x3f). bit 22: r/w arxrst: asynchronous receiver reset. this bit will auto clear when the link layer state machine is idle. bit 21: r/w atxrst: asynchronous transmitter reset. the power-up reset value of this bit is a0o, however, after every bus reset this bit is set (1). this effectively disables the asynchronous transmitter; re-enable the async transmitter by clearing this bit after each bus reset, especially if asynchronous transmission is to be used. bit 20: r/w arxall: receive and filter only response packets. when set (1), all responses are stored. when clear (0), only solicited responses are stored. bit 19..16: r/w maxrc: maximum number of asynchronous transmitter single phase retries bit 15..13: r/w tos: time out seconds, integer of 1 second bit 12..0: r/w tof: time out fractions, integer of 1/8000 second. resets to 0320h, which is 100 milliseconds. 13.3.2 asynchronous rx/tx memory status (asymem) base address: 0x084 treqqidle rrspqf treqqaf treqq5av 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 trspqf trspqaf rreqqe rreqqf rreqqaf rreqq5av rrspqaf rrspqe trspq5av rrspq5av treqqf trspqe treqqe 31 30 sv00918 trspqidle reset value 0x00033333 unused bits read `0'. the information in this register is primarily used for diagnostics. bit 17: r trspqidle: transmitter response queue is idle. indicates that the transfer register for this queue is empty. bit 16: r treqqidle: transmitter request queue is idle. indicates that the transfer register for this queue is empty. bit 15: r rrspqf: receiver response queue full. bit 14: r rrspqaf: receiver response queue almost full (precisely 1 more quadlet available). bit 13: r rrspq5av: receiver response queue at least 5 quadlets available. bit 12: r rrspqe: receiver response queue empty. bit 11: r rreqqf: receiver request queue full. bit 10: r rreqqaf: receiver request queue almost full (precisely 1 more quadlet available). bit 9: r rreqq5av: receiver request queue at least 5 quadlets available. bit 8: r rreqqe: receiver request queue empty. bit 7: r trspqf: transmitter response queue full. bit 6: r trspqaf: transmitter response queue almost full (precisely 1 more quadlet available). bit 5: r trspq5av: transmitter response queue at least 5 quadlets available. bit 4: r trspqe: transmitter response queue empty. bit 3: r treqqf: transmitter request queue full. bit 2: r treqqaf: transmitter request queue almost full (precisely 1 more quadlet available). bit 1: r treqq5av: transmitter request queue at least 5 quadlets available. bit 0: r treqqe: transmitter request queue empty.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 62 13.3.3 asynchronous transmit request next (tx_rq_next) base address: 0x088 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tx_rq_next sv00293 31 30 bit 31..0: w tx_rq_next: first/middle quadlet of packet for transmitter request queue (write only). writing this register will clear the treqqwr flag until the quadlet has been written to its queue. 13.3.4 asynchronous transmit request last (tx_rq_last) base address: 0x08c 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tx_rq_last sv00294 3130 bit 31..0: w tx_rq_last: last quadlet of packet for transmitter request queue (write only). writing this register will clear the treqqwr flag until the quadlet has been written to its queue. 13.3.5 asynchronous transmit response next (tx_rp_next) base address: 0x090 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tx_rp_next sv00295 31 30 bit 31..0: w tx_rp_next: first/middle quadlet of packet for transmitter response queue (write only). writing this register will clear the trspqwr flag until the quadlet has been written to its queue. 13.3.6 asynchronous transmit response last (tx_rp_last) base address: 0x094 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 tx_rp_last sv00296 3130 bit 31..0: w tx_rp_last: last quadlet of packet for transmitter response queue (write only). writing this register will clear the trspqwr flag until the quadlet has been written to its queue.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 63 13.3.7 asynchronous receive request (rreq) base address: 0x098 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rreq sv00297 3130 reset value 0x00000000 bit 31..0: r rreq:quadlet of packet from receiver request queue (transfer register). reading this register will clear the rreqqqav flag until the next received quadlet is available for reading. 13.3.8 asynchronous receive response (rrsp) base address: 0x09c 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rrsp sv00298 31 30 reset value 0x00000000 bit 31..0: r rrsp:quadlet of packet from receiver response queue (transfer register). reading this register will clear the rrspqqav flag until the next received quadlet is available for reading. 13.3.9 asynchronous rx/tx interrupt acknowledge (asyintack) base address: 0x0a0 sv00796 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 timeout rcvdrsp rrspqfull rreqqfull rreqqqav rrspqrderr rreqqrderr rrspqqav sidqav rreqqlastq trspqfull rrspqlastq treqqwrerr trspqwr trspqwrerr treqqfull treqqwr 31 30 reset value 0x00000c00 bit 31..17: r/w unused bits read `0' bit 16: r/w rrspqfull: receiver response queue did become full. write a a1o to this bit to reset the interrupt. bit 15: r/w rreqqfull: receiver request queue did become full. write a a1o to this bit to reset the interrupt. bit 14: r/w sidqav: current quadlet in rreq is selfid data. this bit is set only after a bus reset, not after reception of phy packets other than self ids. this interrupt automatically resets when the quadlet is read. bit 13: r/w rrspqlastq: current quadlet in rrsp is last quadlet of packet. this interrupt automatically resets when the quadlet is read. bit 12: r/w rreqqlastq: current quadlet in rreq is last quadlet of packet. this interrupt automatically resets when the quadlet is read. bit 11: r/w rrspqrderr: receiver response queue read error (transfer error) or bus reset occurred. when set (1), this queue is blocked for read access. write a a1o to this bit to reset the interrupt. bit 10: r/w rreqqrderr: receiver request queue read error (transfer error) or bus reset occurred. when set (1), this queue is blocked for read access. write a a1o to this bit to reset the interrupt. bit 9: r/w rrspqqav: receiver response queue quadlet available (in rrsp). this interrupt automatically resets when the quadlet is read. bit 8: r/w rreqqqav: receiver request queue quadlet available (in rreq). this interrupt automatically resets when the quadlet is read. bit 7: r/w timeout: split transaction response timeout. write a a1o to this bit to reset the interrupt. bit 6: r/w rcvdrsp: solicited response received (within timeout interval). write a a1o to this bit to reset the interrupt. bit 5: r/w trspqfull: transmitter response queue did become full. write a a1o to this bit to reset the interrupt. bit 4: r/w treqqfull: transmitter request queue did become full. write a a1o to this bit to reset the interrupt. bit 3: r/w trspqwrerr: transmitter response queue write error (transfer error). write a a1o to this bit to reset the interrupt. bit 2: r/w treqqwrerr: transmitter request queue write error (transfer error). write a a1o to this bit to reset the interrupt. bit 1: r/w trspqwr: transmitter response queue written (transfer register emptied). write a a1o to this bit to reset the interrup t. bit 0: r/w treqqwr: transmitter request queue written (transfer register emptied). write a a1o to this bit to reset the interrupt .
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 64 13.3.10 asynchronous rx/tx interrupt enable (asyinte) base address: 0x0a4 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 etimeout ercvdrsp errspqfull erreqqfull erreqqqav errspqrderr erreqqrderr errspqqav esidqav erreqqlastq etrspqfull errspqlastq etreqqwrerr etrspqwr etrspqwrerr etreqqfull etreqqwr 31 30 sv00797 reset value 0x00000000 bits16..0 are interrupt enable bits for the asynchronous rx/tx interrupt acknowledge (asyintack). 13.3.11 rdi register base address: 0x0b0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 swpd lpstat epli eloa esca esci sv01779 pli loa sca sci reset value 0x00000000 note: before asserting the rpl bit, swpd or setting the pd pin high, the user should assure that the link chip is in the following state of operation: 1) the isochronous transmit fifo is not receiving data for transmission 2) the isochronous transmitter is disabled 3) no asynchronous packets are being generated for transmission 4) both the async request and response queues are empty bit 31: r/w swpd: software powerdown. writing a 1 to this register bit will cause the link to deactivate its lps pin causing th e phy to turn off the sclk to the link. this, in turn, causes the link chip to go into a low power mode in which only the rdi register is accessible. the function of this bit is identical to that of the hardware pin opdo. when pd is set (1), swpd will be set automatically by the pin state and will cause entry into the power down mode as stated above. do not use both (hardware and software) modes of operation to cause the power down function. use either hardware mode (the pd pin) or the software method (setting / resetting the swpd bit), not both. the pd pin will take precedence over the software method... the link will not come out of pd mode unless the pd pin is deasserted (0). an unused pd pin should be connected to the link chip ground. bit 30: r lpstat: link phy interface status. this bit reflects the status of the lps signal. when the lps signal is active (pulsing) the phy interprets it as indicating that the link power is on and the link is requesting to be activated. the phy, in turn, supplies the sclk to the link, thus giving it the means to become active. the sclk is used by the link to operate most of its internal circuitry. if lps was active and then deactivated, it is a signal to the phy chip that the link desires entry into the power down mode. the lpstat bit continually indicates the status of the lps pin and thus the overall status of the link phy interface. it should also be noted here that a momentary deactivation of the lps signal by the setting of the rpl bit (bit 18 of register 0x004, lnkctl) to cause a link phy interface reset will also be indicated by the lpstat bit. it is suggested that this momentary status change be ignored when the host controller causes a link phy reset through the use of the rpl bit. bit 19: r/w epli: enable the phy link initialized interrupt. leaving this bit in the reset (0) state allows the pli bit to be r ead as a status bit. bit 18: r/w eloa: enable linkon active interrupt. leaving this bit in the reset (0) state allows the loa bit to be read as a sta tus bit. bit 17: r/w esca: enable sclk active interrupt. leaving this bit in the reset (0) state allows the sca bit to be read as a status bit. bit 16: r/w esci: enable sclk inactive interrupt. leaving this bit in the reset (0) state allows the sci bit to be read as a stat us bit.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 65 bit 3: r/w pli: phy link interface initialized interrupt. this interrupt indicates when the phy link initialization routine h as been accomplished. this bit will be set upon completion of the initialization; if enabled, it will cause a host interface interrupt in order to inform the host controller of the completed action. reset of this interrupt requires the writing of a (1) to this bit position. bit 2: r/w loa: linkon active interrupt. this interrupt will become active when a linkon signal is received by the link from th e phy. this bit will remain active as long as the linkon signal is active. when enabled, this bit will set and cause a host interface interrupt when the link detects the presence of a linkon signal from the phy. in practice, the link will be in the power down state when this interrupt occurs (a linkon packet was sent by another node on the bus which desires to communicate with this powered down node). proper servicing of this interrupt will contain a scenario similar to: this node is in power down mode and the host controller has set the eloa bit to enable the interrupt and the phy of this node received a linkon packet from another node requesting this node to power up; (1) the host controller gets the interrupt and makes a decision to power up, (2) the host deasserts swpd (by hardware or software means... see swpd above), (3) the host monitors sca for a o1o state, (4) when sca is true, the host writes a 0 to the eloa bit and then writes a 1 to the loa interrupt bit to cancel the interrupt. the link is now powered up. bit 1: r/w sca: sclk active interrupt. when the sclk signal from the phy to the link is present, this bit is set. if this interru pt has been enabled, the host will receive an interrupt when the sclk becomes active (an example of such use might be during the recovery from a link power down situation). bit 0: r/w sci: sclk inactive interrupt. when the sclk signal is not active, this bit sets. if this interrupt is enabled, when th e sclk ceases to be active, the interrupt will occur. sclk could become inactive due to the phy connected to this link going into power down mode. 13.3.12 shadow register (shadow_reg) base address: 0x0f4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sv01817 byte 0 byte 1 byte 2 byte 3 reset value 0x0f0a0500 bit 31..0: r/w the shadow register is a mechanism that allows a byte (8-bit) or word (16-bit) host interface write quadlets (32-b it) into the av link. bytes or words can be written into the shadow register in any order and then written to the av link by asserting address line a8 with the desired address. for example, if you want to write to transmit request next register (tx_rq_next), and you were using an 8-bit host, then you would write the first three bytes to the shadow register and the fourth byte to the address 0x188 (or 0x189, or 0x18a, or 0x18b). in practice, any write or read with address line a8 not asserted will be directed to the shadow register. to verify the settings of ltlend and datainv, this register is initialized to 0x0f0a0500 on power up. note, unlike the other registers in this device, access to this register should not be addressed with address line a8 = 1.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 66 13.4 indirect address registers 13.4.1 the host interface register set has been extended to provide additional control and data registers for fifo size control and co py protection control registers. these extensions have been implemented via an indirect addressing mechanism. this mechanism allows software written for previous versions of the av link (pdi1394l21 and pdi1394l11) to operate on the PDI1394L41 with minimal changes. to read or write from the indirect memory, you first write the appropriate address into the indirect address register (a8 = 1), then read or write from (or to) the indirect data increment the indirect address by one quadlet. therefore, if you are writing several quadlets to continuous addresses, you will not need to increment the indirect address register. 13.4.2 indirect address register (indaddr) base address: 0x0f8 sv01027 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 indaddr reserved bit 15..0: r/w indirect address: to read or write from the indirect memory, you first write the appropriate address into the indi rect address register (a8 = 1), then read or write from (or to) the indirect data register (inddata, 0x0fc). each write or read (a8 = 1) to the indirect data register (inddata) will automatically increment the indirect address by one quadlet. the following addresses are defined in the indirect address space: table 8. indaddr address and function indaddr function 00x0fc reserved 0x1000x1fc fifo size registers 0x2000x3fc see datasheet addendum 0x4000x4fc see datasheet addendum 0x5000xffff reserved 13.4.3 indirect data register (inddata) base address: 0x0fc sv01764 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 window to the indirect quadlet pointed to by indaddr bit 31..0: r/w quadlet of data pointed to by the indirect address n the indaddr register (0x0f8). note that the indirect address autoincrements on each read or write of the inddata register.
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 67 13.5 indirect address registers the following registers are defined in the indirect address space. access to these registers must be made through the indirect address (indaddr) and indirect data (inddata) registers. 13.5.1 registers for fifo size programming each fifo can be programmed to a certain size with a granularity of 64 quadlets. the size is determined by the values of the ba se_fifo and end_fifo fields of the fifo size registers. the following formula applies: fifo_size = (end_fifo base_fifo + 1) 64 quadlets the fifo's have been implemented on a single memory. the base_fifo and end_fifo fields are sued to determine the physical start and end address of each fifo inside the memory. the start address of a fifo is {fifo_addr[11:6] = base_fifo, fifo_addr[5:0] = 000000}. the end address of a fifo is {fifo_addr[11:6] = end_fifo, fifo_addr[5:0] = 1 11111}. note: the end_fifo must be larger than base_fifo and the hardware does not check for invalid values. 000000 rrsp 000011 000100 rreq 000111 001000 trsp 001011 001100 trsp 001111 & 111111 010000 irx 011111 100000 & 000000 itx 101111 fifo_bank rrspsize: base_fifo rrspsize: end_fifo rreqsize: base_fifo rreqsize: end_fifo trspsize: base_fifo trspsize: end_fifo treqsize: base_fifo treqsize: end_fifo irxsize: base_fifo irxsize: end_fifo itxsize: base_fifo itxsize: end_fifo fields in fifo size registers sv01765 figure 34. reset situation of size programmable fifos 13.5.1.1 asynchronous receive response fifo size (rrspsize) indirect address: 0x100 sv01766 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 base_fifo end_fifo 000000 000011 reset value 0x00000003 bit 31..14 r/w unused bits read `0' bit 13..8 r/w base_fifo: base address of the fifo bit 7, 6 r/w unused bits read `0' bit 5..0 r/w end_fifo: end address of the fifo
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 68 13.5.1.2 asynchronous receive request fifo size (rreqsize) indirect address: 0x104 sv01767 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 base_fifo end_fifo 000100 000111 reset value 0x00000407 bit 31..14 r/w unused bits read `0' bit 13..8 r/w base_fifo: base address of the fifo bit 7, 6 r/w unused bits read `0' bit 5..0 r/w end_fifo: end address of the fifo 13.5.1.3 asynchronous transmit response fifo size (trspsize) indirect address: 0x110 sv01768 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 base_fifo end_fifo 001000 001011 reset value 0x0000080b bit 31..14 r/w unused bits read `0' bit 13..8 r/w base_fifo: base address of the fifo bit 7, 6 r/w unused bits read `0' bit 5..0 r/w end_fifo: end address of the fifo 13.5.1.4 asynchronous transmit request fifo size (treqsize) indirect address: 0x114 sv01769 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 base_fifo end_fifo 001100 001111 reset value 0x00000c0f bit 31..14 r/w unused bits read `0' bit 13..8 r/w base_fifo: base address of the fifo bit 7, 6 r/w unused bits read `0' bit 5..0 r/w end_fifo: end address of the fifo
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 69 13.5.1.5 isochronous receiver fifo size (irxsize) indirect address: 0x120 sv01770 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 base_fifo end_fifo 010000 011111 reset value 0x0000101f bit 31..14 r/w unused bits read `0' bit 13..8 r/w base_fifo: base address of the fifo bit 7, 6 r/w unused bits read `0' bit 5..0 r/w end_fifo: end address of the fifo 13.5.1.6 isochronous transmitter fifo size (itxsize) indirect address: 0x130 sv01771 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 base_fifo end_fifo 100000 101111 reset value 0x0000202f bit 31..14 r/w unused bits read `0' bit 13..8 r/w base_fifo: base address of the fifo bit 7, 6 r/w unused bits read `0' bit 5..0 r/w end_fifo: end address of the fifo
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 70 14.0 dc electrical characteristics table 9. dc electrical characteristics symbol parameter min max unit note v il low input voltage 0.8 v pin categories 1, 2, 3 v ih high input voltage 2.0 v pin categories 1, 2, 3 v it1 + input threshold, rising edge v dd /2 + 0.3 v dd /2 + 0.9 v pin categories 6, 8 low to high transition v it1 input threshold, falling edge v dd /2 0.9 v dd /2 0.3 v pin categories 6, 8 high to low transition v it2 + input threshold, rising edge .42 v dd + 0.9 v pin category 9 low to high transition v it2 input threshold, falling edge .42 v dd + 0.3 v pin category 9 high to low transition v oh1 high output voltage 2.4 v pin category 1 i oh = 4ma i ol = 4ma v ol1 low output voltage 0.4 v pin category 1 i oh = 4ma i ol = 4ma v oh2 high output voltage 2.4 v pin categories 4, 6, 7 i oh = 4ma v ol2 low output voltage 0.4 v pin categories 4, 5, 6, 7 i ol = 4ma i l in p ut leakage current 1 a pin categories 2, 3 v i = 5.5v or 0v i l in ut leakage current 200 a pin category 8 v i = 5.5v or 0v i oz 3-state out p ut current 5 a pin categories 1, 7 v i = 5.5v or 0v i oz 3 - state out ut current 200 a pin category 6 v i = 5.5v or 0v i dd supply current 150 ma under idle conditions, the maximum value is 10 ma 14.1 pin categories table 10. pin categories category 1: input/output category 2: input category 3: input category 4: output category 5: output category 6: input/output category 7: category 8: category 9: hif ad[7:0] hif a[8] resetn cycleout hif intn phy d[0:7] lreq sclk lnkon avxsync hif csn cyclein clk50 phy ctl[0:1] ison av2err0 hif wrn hif wait av2err1 hif mux lps avxvalid avxendpck hif16bit avxemi av xd[7:0] hif ale 1394mode av1err0 avxclk hif rdn av1err1 avxfsync hif d[15:8] hif a[7:0] avxsysync avxsy avxready
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 71 15.0 ac characteristics gnd = 0v, c l = 50pf limits symbol parameter test conditions waveforms t amb = 0 c to +70 c unit min typ max t period (parallel mode) av clock period figure 36 41.67 ns t su av clock setup time figure 36 20 ns t ih av clock input hold time figure 36 3 ns t od av clock output delay time figure 36 3 24 ns t whigh av clock pulse width high figure 36 10 t wlow av clock pulse width low figure 36 10 t pwfs avxfsync pulse width high figure 37 200 300 ns t sup phy-link setup time figure 38 6.0 ns t hp phy-link hold time figure 38 0 ns t sclkper sclk period figure 38 20.343 20.345 20.347 ns t dp phy-link output delay note: c l = 20pf figure 39 2.0 10.0 ns t as host address setup time figure 40 0 ns t ah host address hold time figure 40 0 ns t cl host chip select pulse width low figure 40 115 ns t ch host chip select pulse width high figure 40 42 ns t rp host read pulse width figure 40 115 ns t acc host access time figure 40 115 ns t dh host data hold time figure 40 0 ns t ds host data setup time figure 40 0 ns t dz host data bus release (hi-z) figure 40 15 ns t wrp host write pulse width figure 40 115 ns t wait wait output delay figure 40 10 ns t wwait wait pulse width figure 40 20 ns t cwh cyclein high pulse width figure 41 200 ns t cwl cyclein low pulse width figure 41 200 ns t cp cyclein cycle period figure 41 125 m s t cd cycleout cycle delay figure 42 20 ns t reset reset_n pulse width low figure 43 10 m s t pwale ale pulse width figures 7, 8, 9, 10 20 ns
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 72 16.0 timing diagrams 16.1 av interface operation sv00240 avclk av d[7:0] message invalid data message message invalid data avsync avvalid averr[0] averr[1] asserted in the event of a bus packet crc error asserted in the event of a data block sequence error figure 35. av parallel interface operation diagram 16.2 av interface critical timings sv00688 t whigh t wlow t period t su t ih t od avclk av d [7:0], avvalid, avsync, avendpck sy, fsync, ready valid valid av d [7:0], averr[1:0], avsync, avvalid figure 36. av interface timing diagram sv00890 t pwfs avxfsync figure 37. avxfsync timing diagram
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 73 16.3 phy-link interface critical timings t hp t sup sclk phy d[0:7], phy ctl[0:1] 50% 50% 50% sv00919 t sclkper 50% figure 38. phy d[0:7], phy ctl[0:1] input setup and hold timing waveforms t dp sclk phy d[0:7], phy ctl[0:1], lreq 50% 50% sv00694 figure 39. phy d[0:7], phy ctl[0:1], and lreq output-delay timing waveforms
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 74 16.4 host interface critical timings sv01776 t acc t as hif a[7:0] t ah t as t ah valid valid t dz t cl t rp t wrp read write t dh hif cs_n hif rd_n hif d[7:0] t ds hif wr_n hif d[7:0] valid t ch a8 t as wait t wait a8 wait t wait note: wait line asserts only during read and write cycles in which a8 is asserted. t pwwait figure 40. host interface timing waveforms 16.5 cyclein/cycleout timings sv00696 50% 50% 50% t cwh t cwl cyclein t cp figure 41. cyclein waveform
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 75 sv00697 t cd 50% 50% 50% 50% t cd sclk cyclein cycleout figure 42. cycleout waveforms 16.6 reset timings t reset 50% 50% sv00698 reset_n figure 43. reset_n waveform
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 76 lqfp144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm sot486-1
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 77 notes
philips semiconductors preliminary specification PDI1394L41 1394 content protection av link layer controller 2000 apr 15 78 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 2000 all rights reserved. printed in u.s.a. date of release: 04-00 document order number: 9397 750 07108

data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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